VPOP and VPUSH are floating-point load-store instructions

This commit is contained in:
MerryMage 2016-08-23 14:26:50 +01:00
parent 34cffa86a4
commit 8c7a81a308
3 changed files with 8 additions and 6 deletions

View file

@ -89,8 +89,6 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"),
INST(&V::vfp2_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm"),
INST(&V::vfp2_VSQRT, "VSQRT", "cccc11101D110001dddd101z11M0mmmm"),
INST(&V::vfp2_VPUSH, "VPUSH", "cccc11010D101101dddd101zvvvvvvvv"),
INST(&V::vfp2_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv"),
// VCMP
// VCMPE
// VCVT
@ -100,6 +98,8 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// VSTR
// VSTM
// VSTMDB
INST(&V::vfp2_VPUSH, "VPUSH", "cccc11010D101101dddd101zvvvvvvvv"),
INST(&V::vfp2_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv"),
INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"),
INST(&V::vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv"),
// VLDM

View file

@ -893,6 +893,8 @@ public:
u32 imm32 = imm8 << 2;
return Common::StringFromFormat("vstr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);
}
};
std::string DisassembleArm(u32 instruction) {

View file

@ -357,12 +357,12 @@ struct ArmTranslatorVisitor final {
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
// Floating-point load-store instructions
bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
};
} // namespace Arm