From 8c587df8ce2037d493a86914ae6574fa2fcd34a0 Mon Sep 17 00:00:00 2001
From: MerryMage <MerryMage@users.noreply.github.com>
Date: Fri, 8 Jul 2016 21:38:43 +0800
Subject: [PATCH] Implement thumb1_ADD_imm_t2

---
 src/frontend/decoder/thumb1.h       |  6 +++---
 src/frontend/disassembler_thumb.cpp |  6 +++++-
 src/frontend/translate_thumb.cpp    | 15 ++++++++++++++-
 3 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/src/frontend/decoder/thumb1.h b/src/frontend/decoder/thumb1.h
index 40858a5d..348d140b 100644
--- a/src/frontend/decoder/thumb1.h
+++ b/src/frontend/decoder/thumb1.h
@@ -56,7 +56,7 @@ private:
 };
 
 template <typename V>
-static const std::array<Thumb1Matcher<V>, 16> g_thumb1_instruction_table {{
+static const std::array<Thumb1Matcher<V>, 17> g_thumb1_instruction_table {{
 
 #define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
 
@@ -66,11 +66,11 @@ static const std::array<Thumb1Matcher<V>, 16> g_thumb1_instruction_table {{
     { INST(&V::thumb1_ASR_imm,        "ASR (imm)",                "00010vvvvvmmmddd") },
     { INST(&V::thumb1_ADD_reg_t1,     "ADD (reg, T1)",            "0001100mmmnnnddd") },
     { INST(&V::thumb1_SUB_reg,        "SUB (reg)",                "0001101mmmnnnddd") },
-    { INST(&V::thumb1_ADD_imm,        "ADD (imm)",                "0001110vvvnnnddd") },
+    { INST(&V::thumb1_ADD_imm_t1,     "ADD (imm, T1)",            "0001110vvvnnnddd") },
     { INST(&V::thumb1_SUB_imm,        "SUB (imm)",                "0001111vvvnnnddd") },
     { INST(&V::thumb1_MOV_imm,        "MOV (imm)",                "00100dddvvvvvvvv") },
     { INST(&V::thumb1_CMP_imm,        "CMP (imm)",                "00101nnnvvvvvvvv") },
-    //{ INST(&V::thumb1_ADD_ri,         "ADD (ri)",                 "00110dddvvvvvvvv") },
+    { INST(&V::thumb1_ADD_imm_t2,     "ADD (imm, T2)",            "00110dddvvvvvvvv") },
     //{ INST(&V::thumb1_SUB_ri,         "SUB (ri)",                 "00111dddvvvvvvvv") },
 
      // Data-processing instructions
diff --git a/src/frontend/disassembler_thumb.cpp b/src/frontend/disassembler_thumb.cpp
index 084a643e..b33c1f86 100644
--- a/src/frontend/disassembler_thumb.cpp
+++ b/src/frontend/disassembler_thumb.cpp
@@ -122,7 +122,7 @@ public:
         return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m));
     }
 
-    std::string thumb1_ADD_imm(Imm3 imm3, Reg n, Reg d) {
+    std::string thumb1_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
         return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
     }
 
@@ -138,6 +138,10 @@ public:
         return Common::StringFromFormat("cmp %s, #%u", RegStr(n), imm8);
     }
 
+    std::string thumb1_ADD_imm_t2(Reg d_n, Imm8 imm8) {
+        return Common::StringFromFormat("adds %s, #%u", RegStr(d_n), imm8);
+    }
+
     std::string thumb1_AND_reg(Reg m, Reg d_n) {
         return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
     }
diff --git a/src/frontend/translate_thumb.cpp b/src/frontend/translate_thumb.cpp
index 631010a0..7cad5f31 100644
--- a/src/frontend/translate_thumb.cpp
+++ b/src/frontend/translate_thumb.cpp
@@ -86,7 +86,7 @@ struct TranslatorVisitor final {
         ir.SetVFlag(result.overflow);
         return true;
     }
-    bool thumb1_ADD_imm(Imm3 imm3, Reg n, Reg d) {
+    bool thumb1_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) {
         u32 imm32 = imm3 & 0x7;
         // ADDS <Rd>, <Rn>, #<imm3>
         // Rd can never encode R15.
@@ -130,6 +130,19 @@ struct TranslatorVisitor final {
         ir.SetVFlag(result.overflow);
         return true;
     }
+    bool thumb1_ADD_imm_t2(Reg d_n, Imm8 imm8) {
+        u32 imm32 = imm8 & 0xFF;
+        Reg d = d_n, n = d_n;
+        // ADDS <Rdn>, #<imm8>
+        // Rd can never encode R15.
+        auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(0));
+        ir.SetRegister(d, result.result);
+        ir.SetNFlag(ir.MostSignificantBit(result.result));
+        ir.SetZFlag(ir.IsZero(result.result));
+        ir.SetCFlag(result.carry);
+        ir.SetVFlag(result.overflow);
+        return true;
+    }
 
     bool thumb1_AND_reg(Reg m, Reg d_n) {
         const Reg d = d_n, n = d_n;