A64: Implement UADDL/UADDL2

This commit is contained in:
Lioncash 2018-04-05 09:28:50 -04:00 committed by MerryMage
parent 4b3d70de5f
commit 88d70e3b8a
2 changed files with 17 additions and 1 deletions

View file

@ -687,7 +687,7 @@ INST(SSUBW, "SSUBW, SSUBW2", "0Q001
//INST(SMLSL_vec, "SMLSL, SMLSL2 (vector)", "0Q001110zz1mmmmm101000nnnnnddddd")
//INST(SMULL_vec, "SMULL, SMULL2 (vector)", "0Q001110zz1mmmmm110000nnnnnddddd")
//INST(PMULL, "PMULL, PMULL2", "0Q001110zz1mmmmm111000nnnnnddddd")
//INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd")
INST(UADDL, "UADDL, UADDL2", "0Q101110zz1mmmmm000000nnnnnddddd")
INST(UADDW, "UADDW, UADDW2", "0Q101110zz1mmmmm000100nnnnnddddd")
//INST(USUBL, "USUBL, USUBL2", "0Q101110zz1mmmmm001000nnnnnddddd")
INST(USUBW, "USUBW, USUBW2", "0Q101110zz1mmmmm001100nnnnnddddd")

View file

@ -40,6 +40,22 @@ bool TranslatorVisitor::SSUBW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UADDL(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t part = Q ? 1 : 0;
const IR::U128 operand1 = ir.VectorZeroExtend(esize, Vpart(64, Vn, part));
const IR::U128 operand2 = ir.VectorZeroExtend(esize, Vpart(64, Vm, part));
const IR::U128 result = ir.VectorAdd(esize * 2, operand1, operand2);
V(128, Vd, result);
return true;
}
bool TranslatorVisitor::UADDW(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();