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thumb32: Implement SMLALXY

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This commit is contained in:
Lioncash 2021-02-07 17:37:26 -05:00
parent 8320c56a6e
commit 87cb771bd2
3 changed files with 26 additions and 1 deletions
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2
src/frontend/A32/decoder/thumb32.inc
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@ -284,7 +284,7 @@ INST(thumb32_SMULL, "SMULL", "111110111000nnnnllllhh
INST(thumb32_UMULL, "UMULL", "111110111010nnnnllllhhhh0000mmmm")
//INST(thumb32_UDIV, "UDIV", "111110111011------------1111----")
INST(thumb32_SMLAL, "SMLAL", "111110111100nnnnllllhhhh0000mmmm")
//INST(thumb32_SMLALXY, "SMLALXY", "111110111100------------10------")
INST(thumb32_SMLALXY, "SMLALXY", "111110111100nnnnllllhhhh10NMmmmm")
//INST(thumb32_SMLALD, "SMLALD", "111110111100------------110-----")
//INST(thumb32_SMLSLD, "SMLSLD", "111110111101------------110-----")
INST(thumb32_UMLAL, "UMLAL", "111110111110nnnnllllhhhh0000mmmm")

24
src/frontend/A32/translate/impl/thumb32_long_multiply.cpp
View file

@ -29,6 +29,30 @@ bool ThumbTranslatorVisitor::thumb32_SMLAL(Reg n, Reg dLo, Reg dHi, Reg m) {
return true;
}
bool ThumbTranslatorVisitor::thumb32_SMLALXY(Reg n, Reg dLo, Reg dHi, bool N, bool M, Reg m) {
if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();
}
if (dHi == dLo) {
return UnpredictableInstruction();
}
const IR::U32 n32 = ir.GetRegister(n);
const IR::U32 m32 = ir.GetRegister(m);
const IR::U32 n16 = N ? ir.ArithmeticShiftRight(n32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(n32));
const IR::U32 m16 = M ? ir.ArithmeticShiftRight(m32, ir.Imm8(16), ir.Imm1(0)).result
: ir.SignExtendHalfToWord(ir.LeastSignificantHalf(m32));
const IR::U64 product = ir.SignExtendWordToLong(ir.Mul(n16, m16));
const auto addend = ir.Pack2x32To1x64(ir.GetRegister(dLo), ir.GetRegister(dHi));
const auto result = ir.Add(product, addend);
ir.SetRegister(dLo, ir.LeastSignificantWord(result));
ir.SetRegister(dHi, ir.MostSignificantWord(result).result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_SMULL(Reg n, Reg dLo, Reg dHi, Reg m) {
if (dLo == Reg::PC || dHi == Reg::PC || n == Reg::PC || m == Reg::PC) {
return UnpredictableInstruction();

1
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -118,6 +118,7 @@ struct ThumbTranslatorVisitor final {
// thumb32 long multiply, long multiply accumulate, and divide instructions
bool thumb32_SMLAL(Reg n, Reg dLo, Reg dHi, Reg m);
bool thumb32_SMLALXY(Reg n, Reg dLo, Reg dHi, bool N, bool M, Reg m);
bool thumb32_SMULL(Reg n, Reg dLo, Reg dHi, Reg m);
bool thumb32_UMLAL(Reg n, Reg dLo, Reg dHi, Reg m);
bool thumb32_UMULL(Reg n, Reg dLo, Reg dHi, Reg m);