From 85222e3e6563c1b6b56f0fe25630cba568f59159 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 21 Jun 2020 17:32:38 -0400 Subject: [PATCH] A32: Implement ASIMD VQSHRUN We can leverage ShiftRightNarrowing() to implement this. --- src/frontend/A32/decoder/asimd.inc | 2 +- src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp | 5 +++++ src/frontend/A32/translate/impl/translate_arm.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc index 5d8d0a60..62f5a299 100644 --- a/src/frontend/A32/decoder/asimd.inc +++ b/src/frontend/A32/decoder/asimd.inc @@ -89,7 +89,7 @@ INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd010 INST(asimd_VQSHL, "VQSHL" , "1111001U1Diiiiiidddd011oLQM1mmmm") // ASIMD INST(asimd_VSHRN, "VSHRN", "111100101Diiiiiidddd100000M1mmmm") // ASIMD //INST(asimd_VRSHRN, "VRSHRN", "111100101-vvv-------100001-1----") // ASIMD -//INST(asimd_VQSHRUN, "VQSHRUN", "111100111-vvv-------100000-1----") // ASIMD +INST(asimd_VQSHRUN, "VQSHRUN", "111100111Diiiiiidddd100000M1mmmm") // ASIMD INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD //INST(asimd_VQSHRN, "VQSHRN", "1111001U1-vvv-------100100-1----") // ASIMD INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100101M1mmmm") // ASIMD diff --git a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index c867d8db..518c7c57 100644 --- a/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -286,6 +286,11 @@ bool ArmTranslatorVisitor::asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); } +bool ArmTranslatorVisitor::asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { + return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, + Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Signed); +} + bool ArmTranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { return ShiftRightNarrowing(*this, D, imm6, Vd, M, Vm, Rounding::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed); diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h index 361d13c0..fa2fe7ae 100644 --- a/src/frontend/A32/translate/impl/translate_arm.h +++ b/src/frontend/A32/translate/impl/translate_arm.h @@ -515,6 +515,7 @@ struct ArmTranslatorVisitor final { bool asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm); bool asimd_VQSHL(bool U, bool D, size_t imm6, size_t Vd, bool op, bool L, bool Q, bool M, size_t Vm); bool asimd_VSHRN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); + bool asimd_VQSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm); bool asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, bool to_fixed, bool Q, bool M, size_t Vm);