From 8449deb0bc2d2dadb367e6d59458f54513664c9b Mon Sep 17 00:00:00 2001 From: MerryMage Date: Tue, 12 Jul 2016 13:25:33 +0100 Subject: [PATCH] MSVC support --- CMakeLists.txt | 11 +- src/backend_x64/emit_x64.cpp | 18 +-- src/backend_x64/reg_alloc.h | 2 +- src/common/string_util.h | 10 +- src/frontend/decoder/thumb16.h | 146 +++++++++--------- tests/arm/fuzz_arm.cpp | 5 +- tests/arm/fuzz_thumb.cpp | 6 +- .../dyncom/arm_dyncom_interpreter.cpp | 5 +- 8 files changed, 111 insertions(+), 92 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 50f9f7e1..b3beaa17 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,11 +1,18 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.4.1) project(dynarmic) # Dynarmic project options option(DYNARMIC_USE_SYSTEM_BOOST "Use the system boost libraries" ON) # Compiler flags -add_compile_options(--std=c++14 -Wall -Werror -Wextra -pedantic -Wfatal-errors -Wno-unused-parameter -static -static-libgcc -static-libstdc++) +if (NOT MSVC) + add_compile_options(--std=c++14 -Wall -Werror -Wextra -pedantic -Wfatal-errors -Wno-unused-parameter) + if (ARCHITECTURE_x86_64) + add_compile_options(-msse4.1) + endif() +else() + add_compile_options(/W3 /MP /Zi /Zo /EHsc) +endif() # Arch detection include(CheckSymbolExists) diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp index 22ed5e30..f104e223 100644 --- a/src/backend_x64/emit_x64.cpp +++ b/src/backend_x64/emit_x64.cpp @@ -602,7 +602,7 @@ void EmitX64::EmitReadMemory8(IR::Value* value_) { reg_alloc.HostCall(value, value->GetArg(0).get()); - code->CALL(reinterpret_cast(cb.MemoryRead8)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryRead8)); } void EmitX64::EmitReadMemory16(IR::Value* value_) { @@ -610,7 +610,7 @@ void EmitX64::EmitReadMemory16(IR::Value* value_) { reg_alloc.HostCall(value, value->GetArg(0).get()); - code->CALL(reinterpret_cast(cb.MemoryRead16)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryRead16)); } void EmitX64::EmitReadMemory32(IR::Value* value_) { @@ -618,7 +618,7 @@ void EmitX64::EmitReadMemory32(IR::Value* value_) { reg_alloc.HostCall(value, value->GetArg(0).get()); - code->CALL(reinterpret_cast(cb.MemoryRead32)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryRead32)); } void EmitX64::EmitReadMemory64(IR::Value* value_) { @@ -626,7 +626,7 @@ void EmitX64::EmitReadMemory64(IR::Value* value_) { reg_alloc.HostCall(value, value->GetArg(0).get()); - code->CALL(reinterpret_cast(cb.MemoryRead64)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryRead64)); } void EmitX64::EmitWriteMemory8(IR::Value* value_) { @@ -634,7 +634,7 @@ void EmitX64::EmitWriteMemory8(IR::Value* value_) { reg_alloc.HostCall(nullptr, value->GetArg(0).get(), value->GetArg(1).get()); - code->CALL(reinterpret_cast(cb.MemoryWrite8)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryWrite8)); } void EmitX64::EmitWriteMemory16(IR::Value* value_) { @@ -642,7 +642,7 @@ void EmitX64::EmitWriteMemory16(IR::Value* value_) { reg_alloc.HostCall(nullptr, value->GetArg(0).get(), value->GetArg(1).get()); - code->CALL(reinterpret_cast(cb.MemoryWrite16)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryWrite16)); } void EmitX64::EmitWriteMemory32(IR::Value* value_) { @@ -650,7 +650,7 @@ void EmitX64::EmitWriteMemory32(IR::Value* value_) { reg_alloc.HostCall(nullptr, value->GetArg(0).get(), value->GetArg(1).get()); - code->CALL(reinterpret_cast(cb.MemoryWrite32)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryWrite32)); } void EmitX64::EmitWriteMemory64(IR::Value* value_) { @@ -658,7 +658,7 @@ void EmitX64::EmitWriteMemory64(IR::Value* value_) { reg_alloc.HostCall(nullptr, value->GetArg(0).get(), value->GetArg(1).get()); - code->CALL(reinterpret_cast(cb.MemoryWrite64)); + code->ABI_CallFunction(reinterpret_cast(cb.MemoryWrite64)); } @@ -701,7 +701,7 @@ void EmitX64::EmitTerminalInterpret(IR::Term::Interpret terminal, Arm::LocationD code->MOV(64, R(ABI_PARAM2), Imm64(reinterpret_cast(jit_interface))); code->MOV(32, MJitStateReg(Arm::Reg::PC), R(ABI_PARAM1)); code->MOV(64, R(RSP), MDisp(R15, offsetof(JitState, save_host_RSP))); - code->CALL(reinterpret_cast(cb.InterpreterFallback)); + code->ABI_CallFunction(reinterpret_cast(cb.InterpreterFallback)); code->JMP(routines->RunCodeReturnAddress(), true); // TODO: Check cycles } diff --git a/src/backend_x64/reg_alloc.h b/src/backend_x64/reg_alloc.h index 23317b2d..9e293390 100644 --- a/src/backend_x64/reg_alloc.h +++ b/src/backend_x64/reg_alloc.h @@ -43,7 +43,7 @@ inline bool HostLocIsSpill(HostLoc reg) { return reg >= HostLoc::FirstSpill && reg <= HostLocSpill(SpillCount - 1); } -constexpr std::initializer_list hostloc_any_register = { +const std::initializer_list hostloc_any_register = { HostLoc::RAX, HostLoc::RBX, HostLoc::RCX, diff --git a/src/common/string_util.h b/src/common/string_util.h index 15879417..8e21ef8e 100644 --- a/src/common/string_util.h +++ b/src/common/string_util.h @@ -11,7 +11,15 @@ namespace Dynarmic { namespace Common { -std::string StringFromFormat(const char* format, ...) __attribute__((format(gnu_printf, 1, 2))); +std::string StringFromFormat( +#ifdef _MSC_VER + _Printf_format_string_ +#endif + const char* format, ...) +#ifdef __GNUC__ + __attribute__((format(gnu_printf, 1, 2))) +#endif + ; } // namespace Common } // namespace Dynarmic diff --git a/src/frontend/decoder/thumb16.h b/src/frontend/decoder/thumb16.h index d8ea527f..c2565818 100644 --- a/src/frontend/decoder/thumb16.h +++ b/src/frontend/decoder/thumb16.h @@ -56,100 +56,100 @@ private: }; template -static const std::array, 35> g_thumb16_instruction_table {{ +const std::array, 35> g_thumb16_instruction_table = { #define INST(fn, name, bitstring) detail::detail::GetMatcher(name, bitstring) // Shift (immediate), add, subtract, move and compare instructions - { INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd") }, - { INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd") }, - { INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd") }, - { INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") }, - { INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") }, - { INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd") }, - { INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd") }, - { INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv") }, - { INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv") }, - { INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv") }, - { INST(&V::thumb16_SUB_imm_t2, "SUB (imm, T2)", "00111dddvvvvvvvv") }, + INST(&V::thumb16_LSL_imm, "LSL (imm)", "00000vvvvvmmmddd"), + INST(&V::thumb16_LSR_imm, "LSR (imm)", "00001vvvvvmmmddd"), + INST(&V::thumb16_ASR_imm, "ASR (imm)", "00010vvvvvmmmddd"), + INST(&V::thumb16_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd"), + INST(&V::thumb16_SUB_reg, "SUB (reg)", "0001101mmmnnnddd"), + INST(&V::thumb16_ADD_imm_t1, "ADD (imm, T1)", "0001110vvvnnnddd"), + INST(&V::thumb16_SUB_imm_t1, "SUB (imm, T1)", "0001111vvvnnnddd"), + INST(&V::thumb16_MOV_imm, "MOV (imm)", "00100dddvvvvvvvv"), + INST(&V::thumb16_CMP_imm, "CMP (imm)", "00101nnnvvvvvvvv"), + INST(&V::thumb16_ADD_imm_t2, "ADD (imm, T2)", "00110dddvvvvvvvv"), + INST(&V::thumb16_SUB_imm_t2, "SUB (imm, T2)", "00111dddvvvvvvvv"), // Data-processing instructions - { INST(&V::thumb16_AND_reg, "AND (reg)", "0100000000mmmddd") }, - { INST(&V::thumb16_EOR_reg, "EOR (reg)", "0100000001mmmddd") }, - { INST(&V::thumb16_LSL_reg, "LSL (reg)", "0100000010mmmddd") }, - { INST(&V::thumb16_LSR_reg, "LSR (reg)", "0100000011mmmddd") }, - { INST(&V::thumb16_ASR_reg, "ASR (reg)", "0100000100mmmddd") }, - { INST(&V::thumb16_ADC_reg, "ADC (reg)", "0100000101mmmddd") }, - { INST(&V::thumb16_SBC_reg, "SBC (reg)", "0100000110mmmddd") }, - { INST(&V::thumb16_ROR_reg, "ROR (reg)", "0100000111sssddd") }, - { INST(&V::thumb16_TST_reg, "TST (reg)", "0100001000mmmnnn") }, - { INST(&V::thumb16_RSB_imm, "RSB (imm)", "0100001001nnnddd") }, - { INST(&V::thumb16_CMP_reg_t1, "CMP (reg, T1)", "0100001010mmmnnn") }, - { INST(&V::thumb16_CMN_reg, "CMN (reg)", "0100001011mmmnnn") }, - { INST(&V::thumb16_ORR_reg, "ORR (reg)", "0100001100mmmddd") }, - //{ INST(&V::thumb16_MULS_rr, "MULS (rr)", "0100001101mmmddd") }, - { INST(&V::thumb16_BIC_reg, "BIC (reg)", "0100001110mmmddd") }, - { INST(&V::thumb16_MVN_reg, "MVN (reg)", "0100001111mmmddd") }, + INST(&V::thumb16_AND_reg, "AND (reg)", "0100000000mmmddd"), + INST(&V::thumb16_EOR_reg, "EOR (reg)", "0100000001mmmddd"), + INST(&V::thumb16_LSL_reg, "LSL (reg)", "0100000010mmmddd"), + INST(&V::thumb16_LSR_reg, "LSR (reg)", "0100000011mmmddd"), + INST(&V::thumb16_ASR_reg, "ASR (reg)", "0100000100mmmddd"), + INST(&V::thumb16_ADC_reg, "ADC (reg)", "0100000101mmmddd"), + INST(&V::thumb16_SBC_reg, "SBC (reg)", "0100000110mmmddd"), + INST(&V::thumb16_ROR_reg, "ROR (reg)", "0100000111sssddd"), + INST(&V::thumb16_TST_reg, "TST (reg)", "0100001000mmmnnn"), + INST(&V::thumb16_RSB_imm, "RSB (imm)", "0100001001nnnddd"), + INST(&V::thumb16_CMP_reg_t1, "CMP (reg, T1)", "0100001010mmmnnn"), + INST(&V::thumb16_CMN_reg, "CMN (reg)", "0100001011mmmnnn"), + INST(&V::thumb16_ORR_reg, "ORR (reg)", "0100001100mmmddd"), + //INST(&V::thumb16_MULS_rr, "MULS (rr)", "0100001101mmmddd"), + INST(&V::thumb16_BIC_reg, "BIC (reg)", "0100001110mmmddd"), + INST(&V::thumb16_MVN_reg, "MVN (reg)", "0100001111mmmddd"), // Special data instructions - { INST(&V::thumb16_ADD_reg_t2, "ADD (reg, T2)", "01000100Dmmmmddd") }, // v4T, Low regs: v6T2 - { INST(&V::thumb16_CMP_reg_t2, "CMP (reg, T2)", "01000101Nmmmmnnn") }, // v4T - { INST(&V::thumb16_MOV_reg, "MOV (reg)", "01000110Dmmmmddd") }, // v4T, Low regs: v6 + INST(&V::thumb16_ADD_reg_t2, "ADD (reg, T2)", "01000100Dmmmmddd"), // v4T, Low regs: v6T2 + INST(&V::thumb16_CMP_reg_t2, "CMP (reg, T2)", "01000101Nmmmmnnn"), // v4T + INST(&V::thumb16_MOV_reg, "MOV (reg)", "01000110Dmmmmddd"), // v4T, Low regs: v6 // Store/Load single data item instructions - { INST(&V::thumb16_LDR_literal, "LDR (literal)", "01001tttvvvvvvvv") }, - { INST(&V::thumb16_STR_reg, "STR (reg)", "0101000mmmnnnttt") }, - { INST(&V::thumb16_STRH_reg, "STRH (reg)", "0101001mmmnnnttt") }, - { INST(&V::thumb16_STRB_reg, "STRB (reg)", "0101010mmmnnnttt") }, - //{ INST(&V::thumb16_LDRSB_rrr, "LDRSB (rrr)", "0101011mmmnnnddd") }, - //{ INST(&V::thumb16_LDR_rrr, "LDR (rrr)", "0101100mmmnnnddd") }, - //{ INST(&V::thumb16_LDRH_rrr, "LDRH (rrr)", "0101101mmmnnnddd") }, - //{ INST(&V::thumb16_LDRB_rrr, "LDRB (rrr)", "0101110mmmnnnddd") }, - //{ INST(&V::thumb16_LDRSH_rrr, "LDRSH (rrr)", "0101111mmmnnnddd") }, - { INST(&V::thumb16_LDR_imm_t1, "LDR (imm, T1)", "01101vvvvvnnnttt") }, - //{ INST(&V::thumb16_STRH_rri, "STRH (rri)", "10000vvvvvnnnddd") }, - //{ INST(&V::thumb16_LDRH_rri, "LDRH (rri)", "10001vvvvvnnnddd") }, - //{ INST(&V::thumb16_STR_sp, "STR (SP)", "10010dddvvvvvvvv") }, - //{ INST(&V::thumb16_LDR_sp, "LDR (SP)", "10011dddvvvvvvvv") }, + INST(&V::thumb16_LDR_literal, "LDR (literal)", "01001tttvvvvvvvv"), + INST(&V::thumb16_STR_reg, "STR (reg)", "0101000mmmnnnttt"), + INST(&V::thumb16_STRH_reg, "STRH (reg)", "0101001mmmnnnttt"), + INST(&V::thumb16_STRB_reg, "STRB (reg)", "0101010mmmnnnttt"), + //INST(&V::thumb16_LDRSB_rrr, "LDRSB (rrr)", "0101011mmmnnnddd"), + //INST(&V::thumb16_LDR_rrr, "LDR (rrr)", "0101100mmmnnnddd"), + //INST(&V::thumb16_LDRH_rrr, "LDRH (rrr)", "0101101mmmnnnddd"), + //INST(&V::thumb16_LDRB_rrr, "LDRB (rrr)", "0101110mmmnnnddd"), + //INST(&V::thumb16_LDRSH_rrr, "LDRSH (rrr)", "0101111mmmnnnddd"), + INST(&V::thumb16_LDR_imm_t1, "LDR (imm, T1)", "01101vvvvvnnnttt"), + //INST(&V::thumb16_STRH_rri, "STRH (rri)", "10000vvvvvnnnddd"), + //INST(&V::thumb16_LDRH_rri, "LDRH (rri)", "10001vvvvvnnnddd"), + //INST(&V::thumb16_STR_sp, "STR (SP)", "10010dddvvvvvvvv"), + //INST(&V::thumb16_LDR_sp, "LDR (SP)", "10011dddvvvvvvvv"), // Generate relative address instruction - //{ INST(&V::thumb16_ADR, "ADR", "10100dddvvvvvvvv") }, - //{ INST(&V::thumb16_ADD_sp, "ADD (relative to SP)", "10101dddvvvvvvvv") }, + //INST(&V::thumb16_ADR, "ADR", "10100dddvvvvvvvv"), + //INST(&V::thumb16_ADD_sp, "ADD (relative to SP)", "10101dddvvvvvvvv"), // Miscellaneous 16-bit instructions - //{ INST(&V::thumb16_ADD_spsp, "ADD (imm to SP)", "101100000vvvvvvv") }, // v4T - //{ INST(&V::thumb16_SUB_spsp, "SUB (imm from SP)", "101100001vvvvvvv") }, // v4T - //{ INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd") }, // v6 - //{ INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd") }, // v6 - //{ INST(&V::thumb16_UXTH, "UXTH", "1011001010mmmddd") }, // v6 - //{ INST(&V::thumb16_UXTB, "UXTB", "1011001011mmmddd") }, // v6 - //{ INST(&V::thumb16_PUSH, "PUSH", "1011010rxxxxxxxx") }, // v4T - //{ INST(&V::thumb16_POP, "POP", "1011110rxxxxxxxx") }, // v4T - //{ INST(&V::thumb16_SETEND, "SETEND", "101101100101x000") }, // v6 - //{ INST(&V::thumb16_CPS, "CPS", "10110110011m0aif") }, // v6 - //{ INST(&V::thumb16_REV, "REV", "1011101000nnnddd") }, // v6 - //{ INST(&V::thumb16_REV16, "REV16", "1011101001nnnddd") }, // v6 - //{ INST(&V::thumb16_REVSH, "REVSH", "1011101011nnnddd") }, // v6 - //{ INST(&V::thumb16_BKPT, "BKPT", "10111110xxxxxxxx") }, // v5 + //INST(&V::thumb16_ADD_spsp, "ADD (imm to SP)", "101100000vvvvvvv"), // v4T + //INST(&V::thumb16_SUB_spsp, "SUB (imm from SP)", "101100001vvvvvvv"), // v4T + //INST(&V::thumb16_SXTH, "SXTH", "1011001000mmmddd"), // v6 + //INST(&V::thumb16_SXTB, "SXTB", "1011001001mmmddd"), // v6 + //INST(&V::thumb16_UXTH, "UXTH", "1011001010mmmddd"), // v6 + //INST(&V::thumb16_UXTB, "UXTB", "1011001011mmmddd"), // v6 + //INST(&V::thumb16_PUSH, "PUSH", "1011010rxxxxxxxx"), // v4T + //INST(&V::thumb16_POP, "POP", "1011110rxxxxxxxx"), // v4T + //INST(&V::thumb16_SETEND, "SETEND", "101101100101x000"), // v6 + //INST(&V::thumb16_CPS, "CPS", "10110110011m0aif"), // v6 + //INST(&V::thumb16_REV, "REV", "1011101000nnnddd"), // v6 + //INST(&V::thumb16_REV16, "REV16", "1011101001nnnddd"), // v6 + //INST(&V::thumb16_REVSH, "REVSH", "1011101011nnnddd"), // v6 + //INST(&V::thumb16_BKPT, "BKPT", "10111110xxxxxxxx"), // v5 // Store/Load multiple registers - //{ INST(&V::thumb16_STMIA, "STMIA", "11000nnnxxxxxxxx") }, - //{ INST(&V::thumb16_LDMIA, "LDMIA", "11001nnnxxxxxxxx") }, + //INST(&V::thumb16_STMIA, "STMIA", "11000nnnxxxxxxxx"), + //INST(&V::thumb16_LDMIA, "LDMIA", "11001nnnxxxxxxxx"), // Branch instructions - //{ INST(&V::thumb16_BX, "BX (reg)", "010001110mmmm000") }, // v4T - //{ INST(&V::thumb16_BLX, "BLX (reg)", "010001111mmmm000") }, // v5T - { INST(&V::thumb16_UDF, "UDF", "11011110--------") }, - //{ INST(&V::thumb16_SWI, "SWI", "11011111xxxxxxxx") }, - //{ INST(&V::thumb16_B_cond, "B (cond)", "1101ccccxxxxxxxx") }, - //{ INST(&V::thumb16_B_imm, "B (imm)", "11100xxxxxxxxxxx") }, - //{ INST(&V::thumb16_BLX_suffix, "BLX (imm, suffix)", "11101xxxxxxxxxx0") }, - //{ INST(&V::thumb16_BLX_prefix, "BL/BLX (imm, prefix)", "11110xxxxxxxxxxx") }, - //{ INST(&V::thumb16_BL_suffix, "BL (imm, suffix)", "11111xxxxxxxxxxx") }, + //INST(&V::thumb16_BX, "BX (reg)", "010001110mmmm000"), // v4T + //INST(&V::thumb16_BLX, "BLX (reg)", "010001111mmmm000"), // v5T + INST(&V::thumb16_UDF, "UDF", "11011110--------"), + //INST(&V::thumb16_SWI, "SWI", "11011111xxxxxxxx"), + //INST(&V::thumb16_B_cond, "B (cond)", "1101ccccxxxxxxxx"), + //INST(&V::thumb16_B_imm, "B (imm)", "11100xxxxxxxxxxx"), + //INST(&V::thumb16_BLX_suffix, "BLX (imm, suffix)", "11101xxxxxxxxxx0"), + //INST(&V::thumb16_BLX_prefix, "BL/BLX (imm, prefix)", "11110xxxxxxxxxxx"), + //INST(&V::thumb16_BL_suffix, "BL (imm, suffix)", "11111xxxxxxxxxxx"), #undef INST -}}; +}; template boost::optional&> DecodeThumb16(u16 instruction) { diff --git a/tests/arm/fuzz_arm.cpp b/tests/arm/fuzz_arm.cpp index 525f418a..2b040630 100644 --- a/tests/arm/fuzz_arm.cpp +++ b/tests/arm/fuzz_arm.cpp @@ -6,10 +6,11 @@ #include #include +#include #include -#include +#include "common/bit_util.h" #include "common/common_types.h" #include "frontend/disassembler.h" #include "interface/interface.h" @@ -217,7 +218,7 @@ void FuzzJitArm(const size_t instruction_count, const size_t instructions_to_exe printf("CPSR: %08x %08x %s\n", interp.Cpsr, jit.Cpsr(), interp.Cpsr != jit.Cpsr() ? "*" : ""); #ifdef _MSC_VER - DebugBreak(); + __debugbreak(); #endif FAIL(); } diff --git a/tests/arm/fuzz_thumb.cpp b/tests/arm/fuzz_thumb.cpp index 9c5abebb..3bdb851f 100644 --- a/tests/arm/fuzz_thumb.cpp +++ b/tests/arm/fuzz_thumb.cpp @@ -6,11 +6,11 @@ #include #include +#include #include -#include -#include +#include "common/bit_util.h" #include "common/common_types.h" #include "frontend/disassembler.h" #include "interface/interface.h" @@ -223,7 +223,7 @@ void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_e printf("CPSR: %08x %08x %s\n", interp.Cpsr, jit.Cpsr(), interp.Cpsr != jit.Cpsr() ? "*" : ""); #ifdef _MSC_VER - DebugBreak(); + __debugbreak(); #endif FAIL(); } diff --git a/tests/skyeye_interpreter/dyncom/arm_dyncom_interpreter.cpp b/tests/skyeye_interpreter/dyncom/arm_dyncom_interpreter.cpp index 63092da7..1f9cd4d3 100644 --- a/tests/skyeye_interpreter/dyncom/arm_dyncom_interpreter.cpp +++ b/tests/skyeye_interpreter/dyncom/arm_dyncom_interpreter.cpp @@ -666,7 +666,10 @@ struct arm_inst { unsigned int idx; unsigned int cond; int br; - __extension__ char component[0]; +#ifdef __GNUC__ + __extension__ +#endif + char component[0]; }; struct generic_arm_inst {