Implemented thumb1_ROR_reg

src/backend_x64/emit_x64.cpp

@@ -407,6 +407,45 @@ void EmitX64::EmitArithmeticShiftRight(IR::Value* value_) {
     }
 }
 
+void EmitX64::EmitRotateRight(IR::Value* value_) {
+    auto value = reinterpret_cast<IR::Inst*>(value_);
+    auto carry_inst = FindUseWithOpcode(value, IR::Opcode::GetCarryFromOp);
+
+    if (!carry_inst) {
+        X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX});
+        X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
+
+        // x64 ROR instruction does (shift & 0x1F) for us.
+        code->ROR(32, R(result), R(shift));
+    } else {
+        inhibit_emission.insert(carry_inst);
+
+        X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX});
+        X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value);
+        X64Reg carry = reg_alloc.UseDefRegister(value->GetArg(2).get(), carry_inst);
+
+        // TODO: Optimize
+
+        // if (Rs & 0xFF == 0) goto end;
+        code->TEST(8, R(shift), R(shift));
+        auto Rs_zero = code->J_CC(CC_Z);
+
+        code->AND(32, R(shift), Imm8(0x1F));
+        auto zero_1F = code->J_CC(CC_Z);
+        // if (Rs & 0x1F != 0) {
+        code->ROR(32, R(result), R(shift));
+        code->SETcc(CC_C, R(carry));
+        auto jmp_to_end = code->J();
+        // } else {
+        code->SetJumpTarget(zero_1F);
+        code->BT(32, R(result), Imm8(31));
+        code->SETcc(CC_C, R(carry));
+        // }
+        code->SetJumpTarget(jmp_to_end);
+        code->SetJumpTarget(Rs_zero);
+    }
+}
+
 void EmitX64::EmitAddWithCarry(IR::Value* value_) {
     auto value = reinterpret_cast<IR::Inst*>(value_);
     auto carry_inst = FindUseWithOpcode(value, IR::Opcode::GetCarryFromOp);

src/backend_x64/emit_x64.h

@@ -52,6 +52,7 @@ public:
     void EmitLogicalShiftLeft(IR::Value* value);
     void EmitLogicalShiftRight(IR::Value* value);
     void EmitArithmeticShiftRight(IR::Value* value);
+    void EmitRotateRight(IR::Value* value);
     void EmitAddWithCarry(IR::Value* value);
     void EmitSubWithCarry(IR::Value* value);
     void EmitAnd(IR::Value* value);

src/frontend/decoder/thumb1.h

@@ -56,7 +56,7 @@ private:
 };
 
 template <typename V>
-static const std::array<Thumb1Matcher<V>, 20> g_thumb1_instruction_table {{
+static const std::array<Thumb1Matcher<V>, 21> g_thumb1_instruction_table {{
 
 #define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
 
@@ -81,7 +81,7 @@ static const std::array<Thumb1Matcher<V>, 20> g_thumb1_instruction_table {{
     { INST(&V::thumb1_ASR_reg,        "ASR (reg)",                "0100000100mmmddd") },
     { INST(&V::thumb1_ADC_reg,        "ADC (reg)",                "0100000101mmmddd") },
     { INST(&V::thumb1_SBC_reg,        "SBC (reg)",                "0100000110mmmddd") },
-    //{ INST(&V::thumb1_RORS_rr,        "RORS (rr)",                "0100000111sssddd") },
+    { INST(&V::thumb1_ROR_reg,        "ROR (reg)",                "0100000111sssddd") },
     //{ INST(&V::thumb1_TST_rr,         "TST (rr)",                 "0100001000mmmnnn") },
     //{ INST(&V::thumb1_NEGS_rr,        "NEGS (rr)",                "0100001001mmmddd") },
     //{ INST(&V::thumb1_CMP_rr,         "CMP (rr)",                 "0100001010mmmnnn") },

src/frontend/disassembler_thumb.cpp

@@ -174,6 +174,10 @@ public:
         return Common::StringFromFormat("sbcs %s, %s", RegStr(d_n), RegStr(m));
     }
 
+    std::string thumb1_ROR_reg(Reg m, Reg d_n) {
+        return Common::StringFromFormat("rors %s, %s", RegStr(d_n), RegStr(m));
+    }
+
     std::string thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
         Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
         return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m));

src/frontend/ir/opcodes.inc

@@ -29,6 +29,7 @@ OPCODE(IsZero,                  T::U1,          T::U32
 OPCODE(LogicalShiftLeft,        T::U32,         T::U32,         T::U8,          T::U1           )
 OPCODE(LogicalShiftRight,       T::U32,         T::U32,         T::U8,          T::U1           )
 OPCODE(ArithmeticShiftRight,    T::U32,         T::U32,         T::U8,          T::U1           )
+OPCODE(RotateRight,             T::U32,         T::U32,         T::U8,          T::U1           )
 OPCODE(AddWithCarry,            T::U32,         T::U32,         T::U32,         T::U1           )
 OPCODE(SubWithCarry,            T::U32,         T::U32,         T::U32,         T::U1           )
 OPCODE(And,                     T::U32,         T::U32,         T::U32                          )

src/frontend/ir_emitter.cpp

@@ -99,6 +99,12 @@ IREmitter::ResultAndCarry IREmitter::ArithmeticShiftRight(IR::ValuePtr value_in,
     return {result, carry_out};
 }
 
+IREmitter::ResultAndCarry IREmitter::RotateRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in) {
+    auto result = Inst(IR::Opcode::RotateRight, {value_in, shift_amount, carry_in});
+    auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});
+    return {result, carry_out};
+}
+
 IREmitter::ResultAndCarryAndOverflow IREmitter::AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in) {
     auto result = Inst(IR::Opcode::AddWithCarry, {a, b, carry_in});
     auto carry_out = Inst(IR::Opcode::GetCarryFromOp, {result});

src/frontend/ir_emitter.h

@@ -55,6 +55,7 @@ public:
     ResultAndCarry LogicalShiftLeft(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
     ResultAndCarry LogicalShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
     ResultAndCarry ArithmeticShiftRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
+    ResultAndCarry RotateRight(IR::ValuePtr value_in, IR::ValuePtr shift_amount, IR::ValuePtr carry_in);
     ResultAndCarryAndOverflow AddWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
     ResultAndCarryAndOverflow SubWithCarry(IR::ValuePtr a, IR::ValuePtr b, IR::ValuePtr carry_in);
     IR::ValuePtr And(IR::ValuePtr a, IR::ValuePtr b);

src/frontend/translate_thumb.cpp

@@ -239,6 +239,18 @@ struct TranslatorVisitor final {
         ir.SetVFlag(result.overflow);
         return true;
     }
+    bool thumb1_ROR_reg(Reg m, Reg d_n) {
+        Reg d = d_n, n = d_n;
+        // RORS <Rdn>, <Rm>
+        auto shift_n = ir.LeastSignificantByte(ir.GetRegister(m));
+        auto cpsr_c = ir.GetCFlag();
+        auto result = ir.RotateRight(ir.GetRegister(n), shift_n, cpsr_c);
+        ir.SetRegister(d, result.result);
+        ir.SetNFlag(ir.MostSignificantBit(result.result));
+        ir.SetZFlag(ir.IsZero(result.result));
+        ir.SetCFlag(result.carry);
+        return true;
+    }
 
     bool thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
         Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;