backend/arm64: Initial implementation of register allocator
This commit is contained in:
Merry
merry
parent
3bf2b0aba9
commit
7e046357ff
8 changed files with 646 additions and 15 deletions
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@ -368,6 +368,15 @@ if (ARCHITECTURE STREQUAL "x86_64")
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elseif(ARCHITECTURE STREQUAL "arm64")
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target_link_libraries(dynarmic PRIVATE $<BUILD_INTERFACE:merry::oaknut>)
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target_sources(dynarmic PRIVATE
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backend/arm64/abi.h
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backend/arm64/emit_arm64.cpp
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backend/arm64/emit_arm64.h
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backend/arm64/reg_alloc.cpp
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backend/arm64/reg_alloc.h
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backend/arm64/stack_layout.h
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)
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if ("A32" IN_LIST DYNARMIC_FRONTENDS)
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target_sources(dynarmic PRIVATE
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backend/arm64/a32_address_space.cpp
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@ -376,8 +385,6 @@ elseif(ARCHITECTURE STREQUAL "arm64")
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backend/arm64/a32_interface.cpp
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backend/arm64/a32_jitstate.cpp
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backend/arm64/a32_jitstate.h
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backend/arm64/emit_arm64.cpp
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backend/arm64/emit_arm64.h
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)
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endif()
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@ -5,6 +5,7 @@
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#include "dynarmic/backend/arm64/a32_address_space.h"
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#include "dynarmic/backend/arm64/abi.h"
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#include "dynarmic/backend/arm64/emit_arm64.h"
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#include "dynarmic/frontend/A32/a32_location_descriptor.h"
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#include "dynarmic/frontend/A32/translate/a32_translate.h"
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@ -78,6 +79,8 @@ void A32AddressSpace::EmitPrelude() {
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for (int i = 0; i < 32; i += 2) {
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code.STP(QReg{i}, QReg{i + 1}, SP, PRE_INDEXED, -32);
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}
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code.MOV(Xstate, X1);
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code.MOV(Xhalt, X2);
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code.BR(X0);
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prelude_info.return_from_run_code = code.ptr<void*>();
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@ -106,7 +109,7 @@ EmittedBlockInfo A32AddressSpace::Emit(IR::Block block) {
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mem.unprotect();
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EmittedBlockInfo block_info = EmitArm64(code, std::move(block));
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EmittedBlockInfo block_info = EmitArm64(code, std::move(block), {});
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Link(block_info);
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mem.protect();
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@ -5,12 +5,14 @@
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#pragma once
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#include <array>
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#include <mcl/stdint.hpp>
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#include <oaknut/oaknut.hpp>
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namespace Dynarmic::Backend::Arm64 {
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constexpr u32 ABI_ALL_
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constexpr oaknut::XReg Xstate{28};
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constexpr oaknut::XReg Xhalt{27};
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constexpr oaknut::XReg Xscratch0{16}, Xscratch1{17};
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constexpr oaknut::WReg Wscratch0{16}, Wscratch1{17};
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} // namespace Dynarmic::Backend::Arm64
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@ -5,27 +5,75 @@
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#include "dynarmic/backend/arm64/emit_arm64.h"
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#include <fmt/ostream.h>
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#include <oaknut/oaknut.hpp>
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#include "dynarmic/backend/arm64/a32_jitstate.h"
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#include "dynarmic/backend/arm64/abi.h"
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#include "dynarmic/backend/arm64/emit_context.h"
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#include "dynarmic/backend/arm64/reg_alloc.h"
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#include "dynarmic/ir/basic_block.h"
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#include "dynarmic/ir/microinstruction.h"
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#include "dynarmic/ir/opcodes.h"
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namespace Dynarmic::Backend::Arm64 {
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using namespace oaknut::util;
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EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block) {
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(void)block;
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template<IR::Opcode op>
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void EmitIR(oaknut::CodeGenerator&, EmitContext&, IR::Inst*) {
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ASSERT_FALSE("Unimplemented opcode {}", op);
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}
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template<>
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void EmitIR<IR::Opcode::GetCarryFromOp>(oaknut::CodeGenerator&, EmitContext& ctx, IR::Inst* inst) {
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ASSERT(ctx.reg_alloc.IsValueLive(inst));
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}
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EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const EmitConfig& emit_conf) {
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EmittedBlockInfo ebi;
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const std::vector<int> gpr_order{19, 20, 21, 22, 23, 24, 25, 26, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8};
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const std::vector<int> fpr_order{8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
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RegAlloc reg_alloc{code, gpr_order, fpr_order};
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EmitContext ctx{block, reg_alloc, emit_conf, ebi};
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ebi.entry_point = code.ptr<CodePtr>();
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code.MOV(W0, 8);
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code.STR(W0, X1, offsetof(A32JitState, regs) + 0 * sizeof(u32));
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code.MOV(W0, 2);
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code.STR(W0, X1, offsetof(A32JitState, regs) + 1 * sizeof(u32));
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code.STR(W0, X1, offsetof(A32JitState, regs) + 15 * sizeof(u32));
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for (auto iter = block.begin(); iter != block.end(); ++iter) {
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IR::Inst* inst = &*iter;
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switch (inst->GetOpcode()) {
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#define OPCODE(name, type, ...) \
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case IR::Opcode::name: \
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EmitIR<IR::Opcode::name>(code, ctx, inst); \
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break;
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#define A32OPC(name, type, ...) \
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case IR::Opcode::A32##name: \
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EmitIR<IR::Opcode::A32##name>(code, ctx, inst); \
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break;
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#define A64OPC(name, type, ...) \
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case IR::Opcode::A64##name: \
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EmitIR<IR::Opcode::A64##name>(code, ctx, inst); \
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break;
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#include "dynarmic/ir/opcodes.inc"
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#undef OPCODE
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#undef A32OPC
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#undef A64OPC
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default:
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ASSERT_FALSE("Invalid opcode: {}", inst->GetOpcode());
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break;
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}
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}
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// TODO: Add Cycles
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// TODO: Emit Terminal
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const auto term = block.GetTerminal();
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const IR::Term::LinkBlock* link_block_term = boost::get<IR::Term::LinkBlock>(&term);
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ASSERT(link_block_term);
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code.MOV(Xscratch0, link_block_term->next.Value());
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code.STUR(Xscratch0, Xstate, offsetof(A32JitState, regs) + sizeof(u32) * 15);
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ebi.relocations.emplace_back(Relocation{code.ptr<CodePtr>() - ebi.entry_point, LinkTarget::ReturnFromRunCode});
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code.NOP();
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@ -19,6 +19,8 @@ using CodeGenerator = BasicCodeGenerator<PointerCodeGeneratorPolicy>;
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namespace Dynarmic::IR {
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class Block;
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enum class Opcode;
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class Inst;
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} // namespace Dynarmic::IR
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namespace Dynarmic::Backend::Arm64 {
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@ -40,6 +42,14 @@ struct EmittedBlockInfo {
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std::vector<Relocation> relocations;
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};
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EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block);
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struct EmitConfig {
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};
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struct EmitContext;
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template<IR::Opcode op>
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void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst);
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EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const EmitConfig& emit_conf);
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} // namespace Dynarmic::Backend::Arm64
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278
src/dynarmic/backend/arm64/reg_alloc.cpp
Normal file
278
src/dynarmic/backend/arm64/reg_alloc.cpp
Normal file
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@ -0,0 +1,278 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2022 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "dynarmic/backend/arm64/reg_alloc.h"
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#include <algorithm>
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#include <array>
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#include <mcl/assert.hpp>
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#include <mcl/stdint.hpp>
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namespace Dynarmic::Backend::Arm64 {
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using namespace oaknut::util;
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constexpr size_t spill_offset = offsetof(StackLayout, spill);
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constexpr size_t spill_slot_size = sizeof(decltype(StackLayout::spill)::value_type);
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static bool IsValuelessType(IR::Type type) {
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switch (type) {
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case IR::Type::Table:
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return true;
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default:
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return false;
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}
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}
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IR::Type Argument::GetType() const {
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return value.GetType();
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}
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bool Argument::IsImmediate() const {
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return value.IsImmediate();
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}
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bool Argument::GetImmediateU1() const {
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return value.GetU1();
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}
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u8 Argument::GetImmediateU8() const {
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const u64 imm = value.GetImmediateAsU64();
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ASSERT(imm < 0x100);
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return u8(imm);
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}
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u16 Argument::GetImmediateU16() const {
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const u64 imm = value.GetImmediateAsU64();
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ASSERT(imm < 0x10000);
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return u16(imm);
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}
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u32 Argument::GetImmediateU32() const {
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const u64 imm = value.GetImmediateAsU64();
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ASSERT(imm < 0x100000000);
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return u32(imm);
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}
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u64 Argument::GetImmediateU64() const {
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return value.GetImmediateAsU64();
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}
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IR::Cond Argument::GetImmediateCond() const {
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ASSERT(IsImmediate() && GetType() == IR::Type::Cond);
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return value.GetCond();
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}
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IR::AccType Argument::GetImmediateAccType() const {
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ASSERT(IsImmediate() && GetType() == IR::Type::AccType);
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return value.GetAccType();
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}
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RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
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ArgumentInfo ret = {Argument{*this}, Argument{*this}, Argument{*this}, Argument{*this}};
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for (size_t i = 0; i < inst->NumArgs(); i++) {
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const IR::Value arg = inst->GetArg(i);
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ret[i].value = arg;
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if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
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ASSERT_MSG(ValueLocation(arg.GetInst()), "argument must already been defined");
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ValueInfo(arg.GetInst()).accumulated_uses++;
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}
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}
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return ret;
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}
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bool RegAlloc::IsValueLive(IR::Inst* inst) const {
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return !!ValueLocation(inst);
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}
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template<bool is_vector>
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int RegAlloc::RealizeReadImpl(const IR::Inst* value) {
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constexpr HostLoc::Kind required_kind = is_vector ? HostLoc::Kind::Fpr : HostLoc::Kind::Gpr;
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const auto current_location = ValueLocation(value);
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ASSERT(current_location);
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if (current_location->kind == required_kind) {
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ValueInfo(*current_location).realized = true;
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return current_location->index;
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}
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ASSERT(!ValueInfo(*current_location).realized);
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ASSERT(ValueInfo(*current_location).locked);
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if constexpr (is_vector) {
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const int new_location_index = AllocateRegister(fprs, fpr_order);
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SpillFpr(new_location_index);
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switch (current_location->kind) {
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case HostLoc::Kind::Gpr:
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code.FMOV(oaknut::DReg{new_location_index}, oaknut::XReg{current_location->index});
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break;
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case HostLoc::Kind::Fpr:
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ASSERT_FALSE("Logic error");
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break;
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case HostLoc::Kind::Spill:
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code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + new_location_index * spill_slot_size);
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break;
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}
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fprs[new_location_index] = std::exchange(ValueInfo(*current_location), {});
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fprs[new_location_index].realized = true;
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return new_location_index;
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} else {
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const int new_location_index = AllocateRegister(gprs, gpr_order);
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SpillGpr(new_location_index);
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switch (current_location->kind) {
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case HostLoc::Kind::Gpr:
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ASSERT_FALSE("Logic error");
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break;
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case HostLoc::Kind::Fpr:
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code.FMOV(oaknut::XReg{current_location->index}, oaknut::DReg{new_location_index});
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// ASSERT size fits
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break;
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case HostLoc::Kind::Spill:
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code.LDR(oaknut::XReg{new_location_index}, SP, spill_offset + new_location_index * spill_slot_size);
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break;
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}
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gprs[new_location_index] = std::exchange(ValueInfo(*current_location), {});
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gprs[new_location_index].realized = true;
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return new_location_index;
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}
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}
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template<bool is_vector>
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int RegAlloc::RealizeWriteImpl(const IR::Inst* value) {
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ASSERT(!ValueLocation(value));
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const auto setup_location = [&](HostLocInfo& info) {
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info = {};
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info.values.emplace(value);
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info.locked = true;
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info.realized = true;
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info.expected_uses += value->UseCount();
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};
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if constexpr (is_vector) {
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const int new_location_index = AllocateRegister(fprs, fpr_order);
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SpillFpr(new_location_index);
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setup_location(fprs[new_location_index]);
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return new_location_index;
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} else {
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const int new_location_index = AllocateRegister(gprs, gpr_order);
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SpillGpr(new_location_index);
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setup_location(gprs[new_location_index]);
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return new_location_index;
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}
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}
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template int RegAlloc::RealizeReadImpl<true>(const IR::Inst* value);
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template int RegAlloc::RealizeReadImpl<false>(const IR::Inst* value);
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template int RegAlloc::RealizeWriteImpl<true>(const IR::Inst* value);
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template int RegAlloc::RealizeWriteImpl<false>(const IR::Inst* value);
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void RegAlloc::Unlock(HostLoc host_loc) {
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HostLocInfo& info = ValueInfo(host_loc);
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if (!info.realized) {
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return;
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}
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if (info.accumulated_uses == info.expected_uses) {
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info = {};
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} else {
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info.realized = false;
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info.locked = false;
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}
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}
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int RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const std::vector<int>& order) const {
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const auto empty = std::find_if(order.begin(), order.end(), [&](int i) { return regs[i].values.empty() && !regs[i].locked; });
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if (empty != order.end()) {
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return *empty;
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}
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std::vector<int> candidates;
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std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](int i) { return !regs[i].locked; });
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// TODO: LRU
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std::uniform_int_distribution<size_t> dis{0, candidates.size() - 1};
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return candidates[dis(rand_gen)];
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}
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void RegAlloc::SpillGpr(int index) {
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ASSERT(!gprs[index].locked && !gprs[index].realized);
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if (gprs[index].values.empty()) {
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return;
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}
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const int new_location_index = FindFreeSpill();
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code.STR(oaknut::XReg{index}, SP, spill_offset + new_location_index * spill_slot_size);
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spills[new_location_index] = std::exchange(gprs[index], {});
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}
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void RegAlloc::SpillFpr(int index) {
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ASSERT(!fprs[index].locked && !fprs[index].realized);
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if (fprs[index].values.empty()) {
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return;
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}
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const int new_location_index = FindFreeSpill();
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code.STR(oaknut::QReg{index}, SP, spill_offset + new_location_index * spill_slot_size);
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spills[new_location_index] = std::exchange(fprs[index], {});
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}
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int RegAlloc::FindFreeSpill() const {
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const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
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ASSERT_MSG(iter != spills.end(), "All spill locations are full");
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return static_cast<int>(iter - spills.begin());
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}
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std::optional<HostLoc> RegAlloc::ValueLocation(const IR::Inst* value) const {
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const auto contains_value = [value](const HostLocInfo& info) {
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return info.values.contains(value);
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};
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if (const auto iter = std::find_if(gprs.begin(), gprs.end(), contains_value); iter != gprs.end()) {
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return HostLoc{HostLoc::Kind::Gpr, static_cast<int>(iter - gprs.begin())};
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}
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if (const auto iter = std::find_if(fprs.begin(), fprs.end(), contains_value); iter != fprs.end()) {
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return HostLoc{HostLoc::Kind::Fpr, static_cast<int>(iter - fprs.begin())};
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}
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if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
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return HostLoc{HostLoc::Kind::Spill, static_cast<int>(iter - spills.begin())};
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}
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return std::nullopt;
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}
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HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
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switch (host_loc.kind) {
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case HostLoc::Kind::Gpr:
|
||||
return gprs[static_cast<size_t>(host_loc.index)];
|
||||
case HostLoc::Kind::Fpr:
|
||||
return fprs[static_cast<size_t>(host_loc.index)];
|
||||
case HostLoc::Kind::Spill:
|
||||
return spills[static_cast<size_t>(host_loc.index)];
|
||||
}
|
||||
ASSERT_FALSE("RegAlloc::ValueInfo: Invalid HostLoc::Kind");
|
||||
}
|
||||
|
||||
HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
|
||||
const auto contains_value = [value](const HostLocInfo& info) {
|
||||
return info.values.contains(value);
|
||||
};
|
||||
|
||||
if (const auto iter = std::find_if(gprs.begin(), gprs.end(), contains_value)) {
|
||||
return *iter;
|
||||
}
|
||||
if (const auto iter = std::find_if(fprs.begin(), fprs.end(), contains_value)) {
|
||||
return *iter;
|
||||
}
|
||||
if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value)) {
|
||||
return *iter;
|
||||
}
|
||||
ASSERT_FALSE("RegAlloc::ValueInfo: Value not found");
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::Arm64
|
||||
244
src/dynarmic/backend/arm64/reg_alloc.h
Normal file
244
src/dynarmic/backend/arm64/reg_alloc.h
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2022 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
#include <optional>
|
||||
#include <random>
|
||||
#include <utility>
|
||||
#include <vector>
|
||||
|
||||
#include <mcl/assert.hpp>
|
||||
#include <mcl/stdint.hpp>
|
||||
#include <mcl/type_traits/is_instance_of_template.hpp>
|
||||
#include <oaknut/oaknut.hpp>
|
||||
#include <tsl/robin_set.h>
|
||||
|
||||
#include "dynarmic/backend/arm64/stack_layout.h"
|
||||
#include "dynarmic/ir/cond.h"
|
||||
#include "dynarmic/ir/microinstruction.h"
|
||||
#include "dynarmic/ir/value.h"
|
||||
|
||||
namespace Dynarmic::Backend::Arm64 {
|
||||
|
||||
class RegAlloc;
|
||||
|
||||
struct HostLoc {
|
||||
enum class Kind {
|
||||
Gpr,
|
||||
Fpr,
|
||||
Spill,
|
||||
} kind;
|
||||
int index;
|
||||
};
|
||||
|
||||
struct Argument {
|
||||
public:
|
||||
using copyable_reference = std::reference_wrapper<Argument>;
|
||||
|
||||
IR::Type GetType() const;
|
||||
bool IsImmediate() const;
|
||||
|
||||
bool GetImmediateU1() const;
|
||||
u8 GetImmediateU8() const;
|
||||
u16 GetImmediateU16() const;
|
||||
u32 GetImmediateU32() const;
|
||||
u64 GetImmediateU64() const;
|
||||
IR::Cond GetImmediateCond() const;
|
||||
IR::AccType GetImmediateAccType() const;
|
||||
|
||||
private:
|
||||
friend class RegAlloc;
|
||||
explicit Argument(RegAlloc& reg_alloc)
|
||||
: reg_alloc{reg_alloc} {}
|
||||
|
||||
bool allocated = false;
|
||||
RegAlloc& reg_alloc;
|
||||
IR::Value value;
|
||||
};
|
||||
|
||||
template<typename T>
|
||||
struct RAReg {
|
||||
public:
|
||||
static constexpr bool is_vector = std::is_base_of_v<oaknut::VReg, T>;
|
||||
|
||||
operator T() const { return *reg; }
|
||||
|
||||
template<typename U = T, typename = std::enable_if_t<std::is_same_v<U, oaknut::WReg> && std::is_same_v<T, U>>>
|
||||
operator oaknut::WRegWsp() const {
|
||||
return *reg;
|
||||
}
|
||||
|
||||
template<typename U = T, typename = std::enable_if_t<std::is_same_v<U, oaknut::XReg> && std::is_same_v<T, U>>>
|
||||
operator oaknut::XRegSp() const {
|
||||
return *reg;
|
||||
}
|
||||
|
||||
T operator*() const { return *reg; }
|
||||
|
||||
~RAReg();
|
||||
|
||||
private:
|
||||
friend class RegAlloc;
|
||||
explicit RAReg(RegAlloc& reg_alloc, bool write, const IR::Inst* value)
|
||||
: reg_alloc{reg_alloc}, write{write}, value{value} {}
|
||||
|
||||
void Realize();
|
||||
|
||||
RegAlloc& reg_alloc;
|
||||
bool write;
|
||||
const IR::Inst* value;
|
||||
std::optional<T> reg;
|
||||
};
|
||||
|
||||
struct HostLocInfo {
|
||||
tsl::robin_set<const IR::Inst*> values;
|
||||
bool locked = false;
|
||||
bool realized = false;
|
||||
size_t accumulated_uses = 0;
|
||||
size_t expected_uses = 0;
|
||||
};
|
||||
|
||||
class RegAlloc {
|
||||
public:
|
||||
using ArgumentInfo = std::array<Argument, IR::max_arg_count>;
|
||||
|
||||
explicit RegAlloc(oaknut::CodeGenerator& code, std::vector<int> gpr_order, std::vector<int> fpr_order)
|
||||
: code{code}, gpr_order{gpr_order}, fpr_order{fpr_order}, rand_gen{std::random_device{}()} {}
|
||||
|
||||
ArgumentInfo GetArgumentInfo(IR::Inst* inst);
|
||||
bool IsValueLive(IR::Inst* inst) const;
|
||||
|
||||
auto ReadX(Argument& arg) { return RAReg<oaknut::XReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
auto ReadW(Argument& arg) { return RAReg<oaknut::WReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
|
||||
auto ReadQ(Argument& arg) { return RAReg<oaknut::QReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
auto ReadD(Argument& arg) { return RAReg<oaknut::DReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
auto ReadS(Argument& arg) { return RAReg<oaknut::SReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
auto ReadH(Argument& arg) { return RAReg<oaknut::HReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
auto ReadB(Argument& arg) { return RAReg<oaknut::BReg>{*this, false, PreReadImpl(arg.value)}; }
|
||||
|
||||
template<size_t size>
|
||||
auto ReadReg(Argument& arg) {
|
||||
if constexpr (size == 64) {
|
||||
return ReadX(arg);
|
||||
} else if constexpr (size == 32) {
|
||||
return ReadW(arg);
|
||||
} else {
|
||||
ASSERT_FALSE("Invalid size to ReadReg {}", size);
|
||||
}
|
||||
}
|
||||
|
||||
template<size_t size>
|
||||
auto ReadVec(Argument& arg) {
|
||||
if constexpr (size == 128) {
|
||||
return ReadQ(arg);
|
||||
} else if constexpr (size == 64) {
|
||||
return ReadD(arg);
|
||||
} else if constexpr (size == 32) {
|
||||
return ReadS(arg);
|
||||
} else if constexpr (size == 16) {
|
||||
return ReadH(arg);
|
||||
} else if constexpr (size == 8) {
|
||||
return ReadB(arg);
|
||||
} else {
|
||||
ASSERT_FALSE("Invalid size to ReadVec {}", size);
|
||||
}
|
||||
}
|
||||
|
||||
auto WriteX(IR::Inst* inst) { return RAReg<oaknut::XReg>{*this, true, inst}; }
|
||||
auto WriteW(IR::Inst* inst) { return RAReg<oaknut::WReg>{*this, true, inst}; }
|
||||
|
||||
auto WriteQ(IR::Inst* inst) { return RAReg<oaknut::QReg>{*this, true, inst}; }
|
||||
auto WriteD(IR::Inst* inst) { return RAReg<oaknut::DReg>{*this, true, inst}; }
|
||||
auto WriteS(IR::Inst* inst) { return RAReg<oaknut::SReg>{*this, true, inst}; }
|
||||
auto WriteH(IR::Inst* inst) { return RAReg<oaknut::HReg>{*this, true, inst}; }
|
||||
auto WriteB(IR::Inst* inst) { return RAReg<oaknut::BReg>{*this, true, inst}; }
|
||||
|
||||
template<size_t size>
|
||||
auto WriteReg(IR::Inst* inst) {
|
||||
if constexpr (size == 64) {
|
||||
return WriteX(inst);
|
||||
} else if constexpr (size == 32) {
|
||||
return WriteW(inst);
|
||||
} else {
|
||||
ASSERT_FALSE("Invalid size to WriteReg {}", size);
|
||||
}
|
||||
}
|
||||
|
||||
template<size_t size>
|
||||
auto WriteVec(IR::Inst* inst) {
|
||||
if constexpr (size == 128) {
|
||||
return WriteQ(inst);
|
||||
} else if constexpr (size == 64) {
|
||||
return WriteD(inst);
|
||||
} else if constexpr (size == 32) {
|
||||
return WriteS(inst);
|
||||
} else if constexpr (size == 16) {
|
||||
return WriteH(inst);
|
||||
} else if constexpr (size == 8) {
|
||||
return WriteB(inst);
|
||||
} else {
|
||||
ASSERT_FALSE("Invalid size to WriteVec {}", size);
|
||||
}
|
||||
}
|
||||
|
||||
void SpillAll();
|
||||
|
||||
template<typename... Ts>
|
||||
static void Realize(Ts&... rs) {
|
||||
static_assert((mcl::is_instance_of_template<RAReg, Ts>() && ...));
|
||||
(rs.Realize(), ...);
|
||||
}
|
||||
|
||||
private:
|
||||
template<typename>
|
||||
friend struct RAReg;
|
||||
|
||||
const IR::Inst* PreReadImpl(const IR::Value& value) {
|
||||
ValueInfo(value.GetInst()).locked = true;
|
||||
return value.GetInst();
|
||||
}
|
||||
|
||||
template<bool is_vector>
|
||||
int RealizeReadImpl(const IR::Inst* value);
|
||||
template<bool is_vector>
|
||||
int RealizeWriteImpl(const IR::Inst* value);
|
||||
void Unlock(HostLoc host_loc);
|
||||
|
||||
int AllocateRegister(const std::array<HostLocInfo, 32>& regs, const std::vector<int>& order) const;
|
||||
void SpillGpr(int index);
|
||||
void SpillFpr(int index);
|
||||
int FindFreeSpill() const;
|
||||
|
||||
std::optional<HostLoc> ValueLocation(const IR::Inst* value) const;
|
||||
HostLocInfo& ValueInfo(HostLoc host_loc);
|
||||
HostLocInfo& ValueInfo(const IR::Inst* value);
|
||||
|
||||
oaknut::CodeGenerator& code;
|
||||
std::vector<int> gpr_order;
|
||||
std::vector<int> fpr_order;
|
||||
|
||||
std::array<HostLocInfo, 32> gprs;
|
||||
std::array<HostLocInfo, 32> fprs;
|
||||
std::array<HostLocInfo, SpillCount> spills;
|
||||
|
||||
mutable std::mt19937 rand_gen;
|
||||
};
|
||||
|
||||
template<typename T>
|
||||
RAReg<T>::~RAReg() {
|
||||
if (reg) {
|
||||
reg_alloc.Unlock(HostLoc{is_vector ? HostLoc::Kind::Fpr : HostLoc::Kind::Gpr, reg->index()});
|
||||
}
|
||||
}
|
||||
|
||||
template<typename T>
|
||||
void RAReg<T>::Realize() {
|
||||
reg = T{write ? reg_alloc.RealizeWriteImpl<is_vector>(value) : reg_alloc.RealizeReadImpl<is_vector>(value)};
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::Backend::Arm64
|
||||
39
src/dynarmic/backend/arm64/stack_layout.h
Normal file
39
src/dynarmic/backend/arm64/stack_layout.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2022 MerryMage
|
||||
* SPDX-License-Identifier: 0BSD
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <array>
|
||||
|
||||
#include <mcl/stdint.hpp>
|
||||
|
||||
namespace Dynarmic::Backend::Arm64 {
|
||||
|
||||
constexpr size_t SpillCount = 64;
|
||||
|
||||
#ifdef _MSC_VER
|
||||
# pragma warning(push)
|
||||
# pragma warning(disable : 4324) // Structure was padded due to alignment specifier
|
||||
#endif
|
||||
|
||||
struct alignas(16) StackLayout {
|
||||
s64 cycles_remaining;
|
||||
s64 cycles_to_run;
|
||||
|
||||
std::array<std::array<u64, 2>, SpillCount> spill;
|
||||
|
||||
u32 save_host_fpcr;
|
||||
u32 save_host_fpsr;
|
||||
|
||||
bool check_bit;
|
||||
};
|
||||
|
||||
#ifdef _MSC_VER
|
||||
# pragma warning(pop)
|
||||
#endif
|
||||
|
||||
static_assert(sizeof(StackLayout) % 16 == 0);
|
||||
|
||||
} // namespace Dynarmic::Backend::Arm64
|
||||
Loading…
Reference in a new issue