diff --git a/src/frontend/A32/decoder/thumb32.inc b/src/frontend/A32/decoder/thumb32.inc
index 0179bce3..36aeb21d 100644
--- a/src/frontend/A32/decoder/thumb32.inc
+++ b/src/frontend/A32/decoder/thumb32.inc
@@ -161,11 +161,11 @@ INST(thumb32_LDRSB_imm8,     "LDRSB (imm8)",             "111110010001nnnntttt1P
 INST(thumb32_LDRSB_imm12,    "LDRSB (imm12)",            "111110011001nnnnttttiiiiiiiiiiii")
 
 // Load Halfword and Memory Hints
-//INST(thumb32_LDRH_lit,       "LDRH (lit)",               "11111000-0111111----------------")
-//INST(thumb32_LDRH_reg,       "LDRH (reg)",               "111110000011--------000000------")
-//INST(thumb32_LDRHT,          "LDRHT",                    "111110000011--------1110--------")
-//INST(thumb32_LDRH_imm8,      "LDRH (imm8)",              "111110000011--------1-----------")
-//INST(thumb32_LDRH_imm12,     "LDRH (imm12)",             "111110001011--------------------")
+INST(thumb32_LDRH_lit,       "LDRH (lit)",               "11111000U0111111ttttiiiiiiiiiiii")
+INST(thumb32_LDRH_reg,       "LDRH (reg)",               "111110000011nnnntttt000000iimmmm")
+INST(thumb32_LDRHT,          "LDRHT",                    "111110000011nnnntttt1110iiiiiiii")
+INST(thumb32_LDRH_imm8,      "LDRH (imm8)",              "111110000011nnnntttt1PUWiiiiiiii")
+INST(thumb32_LDRH_imm12,     "LDRH (imm12)",             "111110001011nnnnttttiiiiiiiiiiii")
 //INST(thumb32_LDRSH_lit,      "LDRSH (lit)",              "11111001-0111111----------------")
 //INST(thumb32_LDRSH_reg,      "LDRSH (reg)",              "111110010011--------000000------")
 //INST(thumb32_LDRSHT,         "LDRSHT",                   "111110010011--------1110--------")
diff --git a/src/frontend/A32/translate/impl/thumb32_load_halfword.cpp b/src/frontend/A32/translate/impl/thumb32_load_halfword.cpp
index 5f4e4104..73b07238 100644
--- a/src/frontend/A32/translate/impl/thumb32_load_halfword.cpp
+++ b/src/frontend/A32/translate/impl/thumb32_load_halfword.cpp
@@ -7,5 +7,80 @@
 
 namespace Dynarmic::A32 {
 
+bool ThumbTranslatorVisitor::thumb32_LDRH_lit(bool U, Reg t, Imm<12> imm12) {
+    const auto imm32 = imm12.ZeroExtend();
+    const auto base = ir.AlignPC(4);
+    const auto address = U ? (base + imm32) : (base - imm32);
+    const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(ir.Imm32(address)));
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRH_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
+    if (m == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    const IR::U32 reg_m = ir.GetRegister(m);
+    const IR::U32 reg_n = ir.GetRegister(n);
+    const IR::U32 offset = ir.LogicalShiftLeft(reg_m, ir.Imm8(imm2.ZeroExtend<u8>()));
+    const IR::U32 address = ir.Add(reg_n, offset);
+    const IR::U32 data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRH_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
+    if (!P && !W) {
+        return UndefinedInstruction();
+    }
+    if (t == Reg::PC && W) {
+        return UnpredictableInstruction();
+    }
+    if (W && n == t) {
+        return UnpredictableInstruction();
+    }
+
+    const u32 imm32 = imm8.ZeroExtend();
+    const IR::U32 reg_n = ir.GetRegister(n);
+    const IR::U32 offset_address = U ? ir.Add(reg_n, ir.Imm32(imm32))
+                                     : ir.Sub(reg_n, ir.Imm32(imm32));
+    const IR::U32 address = P ? offset_address
+                              : reg_n;
+    const IR::U32 data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+
+    if (W) {
+        ir.SetRegister(n, offset_address);
+    }
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRH_imm12(Reg n, Reg t, Imm<12> imm12) {
+    const auto imm32 = imm12.ZeroExtend();
+    const auto reg_n = ir.GetRegister(n);
+    const auto address = ir.Add(reg_n, ir.Imm32(imm32));
+    const auto data = ir.ZeroExtendHalfToWord(ir.ReadMemory16(address));
+
+    ir.SetRegister(t, data);
+    return true;
+}
+
+bool ThumbTranslatorVisitor::thumb32_LDRHT(Reg n, Reg t, Imm<8> imm8) {
+    // TODO: Add an unpredictable instruction path if this
+    //       is executed in hypervisor mode if we ever support
+    //       privileged execution levels.
+
+    if (t == Reg::PC) {
+        return UnpredictableInstruction();
+    }
+
+    // Treat it as a normal LDRH, given we don't support
+    // execution levels other than EL0 currently.
+    return thumb32_LDRH_imm8(n, t, true, true, false, imm8);
+}
 
 } // namespace Dynarmic::A32
diff --git a/src/frontend/A32/translate/impl/translate_thumb.h b/src/frontend/A32/translate/impl/translate_thumb.h
index 0bbe6e28..045432f4 100644
--- a/src/frontend/A32/translate/impl/translate_thumb.h
+++ b/src/frontend/A32/translate/impl/translate_thumb.h
@@ -267,6 +267,13 @@ struct ThumbTranslatorVisitor final {
     bool thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12);
     bool thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8);
 
+    // thumb32 load halfword instructions
+    bool thumb32_LDRH_lit(bool U, Reg t, Imm<12> imm12);
+    bool thumb32_LDRH_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
+    bool thumb32_LDRH_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
+    bool thumb32_LDRH_imm12(Reg n, Reg t, Imm<12> imm12);
+    bool thumb32_LDRHT(Reg n, Reg t, Imm<8> imm8);
+
     // thumb32 load word instructions
     bool thumb32_LDR_lit(bool U, Reg t, Imm<12> imm12);
     bool thumb32_LDR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);