suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement CMHI (register, scalar)

Browse source
This commit is contained in:
Lioncash 2018-04-15 05:27:37 -04:00 committed by MerryMage
parent c18b20b8d1
commit 78bb12276a
2 changed files with 9 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -456,7 +456,7 @@ INST(ADD_1, "ADD (vector)", "01011
//INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd") //INST(SQDMULH_vec_1, "SQDMULH (vector)", "01011110zz1mmmmm101101nnnnnddddd")
//INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd") //INST(UQADD_1, "UQADD", "01111110zz1mmmmm000011nnnnnddddd")
//INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd") //INST(UQSUB_1, "UQSUB", "01111110zz1mmmmm001011nnnnnddddd")
//INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd") INST(CMHI_1, "CMHI (register)", "01111110zz1mmmmm001101nnnnnddddd")
//INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd") //INST(CMHS_1, "CMHS (register)", "01111110zz1mmmmm001111nnnnnddddd")
//INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd") //INST(USHL_1, "USHL", "01111110zz1mmmmm010001nnnnnddddd")
//INST(UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd") //INST(UQSHL_reg_1, "UQSHL (register)", "01111110zz1mmmmm010011nnnnnddddd")

9
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -12,6 +12,7 @@ namespace {
enum class ComparisonType { enum class ComparisonType {
GE, GE,
GT, GT,
HI,
}; };
bool ScalarCompare(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, ComparisonType type) { bool ScalarCompare(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, ComparisonType type) {
@ -30,8 +31,10 @@ bool ScalarCompare(TranslatorVisitor& v, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Co
case ComparisonType::GE: case ComparisonType::GE:
return v.ir.VectorGreaterEqualSigned(esize, operand1, operand2); return v.ir.VectorGreaterEqualSigned(esize, operand1, operand2);
case ComparisonType::GT: case ComparisonType::GT:
default:
return v.ir.VectorGreaterSigned(esize, operand1, operand2); return v.ir.VectorGreaterSigned(esize, operand1, operand2);
case ComparisonType::HI:
default:
return v.ir.VectorGreaterUnsigned(esize, operand1, operand2);
} }
}(); }();
@ -62,6 +65,10 @@ bool TranslatorVisitor::CMGT_reg_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return ScalarCompare(*this, size, Vm, Vn, Vd, ComparisonType::GT); return ScalarCompare(*this, size, Vm, Vn, Vd, ComparisonType::GT);
} }
bool TranslatorVisitor::CMHI_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return ScalarCompare(*this, size, Vm, Vn, Vd, ComparisonType::HI);
}
bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::SUB_1(Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size != 0b11) { if (size != 0b11) {
return ReservedValue(); return ReservedValue();