From 78b4ba10c930e7bb2d9b358916467f73053d45c7 Mon Sep 17 00:00:00 2001 From: Merry Date: Tue, 19 Apr 2022 15:36:26 +0100 Subject: [PATCH] Migrate to mcl --- src/dynarmic/CMakeLists.txt | 8 - src/dynarmic/backend/x64/a32_emit_x64.cpp | 20 +- src/dynarmic/backend/x64/a32_interface.cpp | 12 +- src/dynarmic/backend/x64/a32_jitstate.cpp | 35 +- src/dynarmic/backend/x64/a32_jitstate.h | 2 +- src/dynarmic/backend/x64/a64_emit_x64.cpp | 7 +- src/dynarmic/backend/x64/a64_interface.cpp | 9 +- src/dynarmic/backend/x64/a64_jitstate.cpp | 5 +- src/dynarmic/backend/x64/a64_jitstate.h | 3 +- src/dynarmic/backend/x64/abi.cpp | 6 +- src/dynarmic/backend/x64/abi.h | 3 +- src/dynarmic/backend/x64/block_of_code.cpp | 8 +- src/dynarmic/backend/x64/block_of_code.h | 2 +- .../backend/x64/block_range_information.cpp | 3 +- src/dynarmic/backend/x64/callback.h | 3 +- src/dynarmic/backend/x64/constant_pool.cpp | 3 +- src/dynarmic/backend/x64/constant_pool.h | 3 +- src/dynarmic/backend/x64/constants.h | 25 +- src/dynarmic/backend/x64/devirtualize.h | 12 +- src/dynarmic/backend/x64/emit_x64.cpp | 36 +- src/dynarmic/backend/x64/emit_x64.h | 6 +- src/dynarmic/backend/x64/emit_x64_aes.cpp | 3 +- .../backend/x64/emit_x64_data_processing.cpp | 25 +- .../backend/x64/emit_x64_floating_point.cpp | 4 +- .../backend/x64/emit_x64_memory.cpp.inc | 34 +- src/dynarmic/backend/x64/emit_x64_memory.h | 7 +- .../backend/x64/emit_x64_saturation.cpp | 6 +- src/dynarmic/backend/x64/emit_x64_vector.cpp | 58 +-- .../x64/emit_x64_vector_floating_point.cpp | 6 +- .../x64/emit_x64_vector_saturation.cpp | 3 +- src/dynarmic/backend/x64/exception_handler.h | 2 +- .../backend/x64/exception_handler_macos.cpp | 10 +- .../backend/x64/exception_handler_posix.cpp | 11 +- .../backend/x64/exception_handler_windows.cpp | 13 +- .../backend/x64/exclusive_monitor.cpp | 2 +- src/dynarmic/backend/x64/host_feature.h | 2 +- src/dynarmic/backend/x64/hostloc.h | 5 +- src/dynarmic/backend/x64/nzcv_util.h | 19 +- src/dynarmic/backend/x64/oparg.h | 3 +- src/dynarmic/backend/x64/perf_map.cpp | 3 +- src/dynarmic/backend/x64/perf_map.h | 4 +- src/dynarmic/backend/x64/reg_alloc.cpp | 2 +- src/dynarmic/backend/x64/reg_alloc.h | 2 +- src/dynarmic/backend/x64/stack_layout.h | 2 +- src/dynarmic/common/assert.cpp | 21 - src/dynarmic/common/assert.h | 71 ---- src/dynarmic/common/atomic.h | 2 +- src/dynarmic/common/bit_util.h | 248 ------------ src/dynarmic/common/cast_util.h | 27 -- src/dynarmic/common/common_types.h | 28 -- src/dynarmic/common/crypto/aes.cpp | 2 +- src/dynarmic/common/crypto/aes.h | 2 +- src/dynarmic/common/crypto/crc32.cpp | 2 +- src/dynarmic/common/crypto/crc32.h | 2 +- src/dynarmic/common/crypto/sm4.cpp | 2 +- src/dynarmic/common/crypto/sm4.h | 2 +- src/dynarmic/common/fp/fpcr.h | 59 +-- src/dynarmic/common/fp/fpsr.h | 48 +-- src/dynarmic/common/fp/fused.cpp | 4 +- src/dynarmic/common/fp/info.h | 6 +- src/dynarmic/common/fp/mantissa_util.h | 11 +- src/dynarmic/common/fp/op/FPConvert.cpp | 23 +- src/dynarmic/common/fp/op/FPMulAdd.cpp | 3 +- src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp | 3 +- src/dynarmic/common/fp/op/FPRecipEstimate.cpp | 5 +- src/dynarmic/common/fp/op/FPRecipExponent.cpp | 13 +- src/dynarmic/common/fp/op/FPRoundInt.cpp | 15 +- src/dynarmic/common/fp/op/FPRoundInt.h | 2 +- src/dynarmic/common/fp/op/FPToFixed.cpp | 20 +- src/dynarmic/common/fp/op/FPToFixed.h | 2 +- src/dynarmic/common/fp/process_exception.cpp | 3 +- src/dynarmic/common/fp/process_nan.cpp | 7 +- src/dynarmic/common/fp/unpacked.cpp | 19 +- src/dynarmic/common/fp/unpacked.h | 6 +- src/dynarmic/common/intrusive_list.h | 379 ------------------ src/dynarmic/common/iterator_util.h | 35 -- src/dynarmic/common/llvm_disassemble.cpp | 9 +- src/dynarmic/common/llvm_disassemble.h | 2 +- src/dynarmic/common/macro_util.h | 15 - src/dynarmic/common/math_util.h | 2 +- src/dynarmic/common/safe_ops.h | 19 +- src/dynarmic/common/scope_exit.h | 86 ---- src/dynarmic/common/u128.cpp | 3 +- src/dynarmic/common/u128.h | 13 +- src/dynarmic/common/unlikely.h | 12 - src/dynarmic/common/x64_disassemble.cpp | 3 +- src/dynarmic/common/x64_disassemble.h | 2 +- src/dynarmic/frontend/A32/FPSCR.h | 51 +-- src/dynarmic/frontend/A32/ITState.h | 15 +- src/dynarmic/frontend/A32/PSR.h | 57 +-- src/dynarmic/frontend/A32/a32_ir_emitter.cpp | 3 +- src/dynarmic/frontend/A32/a32_ir_emitter.h | 3 +- .../frontend/A32/a32_location_descriptor.h | 3 +- src/dynarmic/frontend/A32/a32_types.cpp | 4 +- src/dynarmic/frontend/A32/a32_types.h | 5 +- src/dynarmic/frontend/A32/decoder/arm.h | 7 +- src/dynarmic/frontend/A32/decoder/asimd.h | 7 +- src/dynarmic/frontend/A32/decoder/thumb16.h | 3 +- src/dynarmic/frontend/A32/decoder/thumb32.h | 3 +- src/dynarmic/frontend/A32/decoder/vfp.h | 3 +- .../frontend/A32/disassembler/disassembler.h | 2 +- .../A32/disassembler/disassembler_arm.cpp | 31 +- .../A32/disassembler/disassembler_thumb.cpp | 4 +- .../frontend/A32/translate/a32_translate.h | 3 +- .../A32/translate/conditional_state.cpp | 5 +- .../A32/translate/conditional_state.h | 2 +- .../A32/translate/impl/a32_branch.cpp | 9 +- .../A32/translate/impl/a32_translate_impl.cpp | 3 +- .../A32/translate/impl/a32_translate_impl.h | 24 +- .../impl/asimd_load_store_structures.cpp | 31 +- .../A32/translate/impl/asimd_misc.cpp | 12 +- .../impl/asimd_one_reg_modified_immediate.cpp | 7 +- .../A32/translate/impl/asimd_three_regs.cpp | 57 +-- .../translate/impl/asimd_two_regs_misc.cpp | 61 +-- .../translate/impl/asimd_two_regs_scalar.cpp | 15 +- .../translate/impl/asimd_two_regs_shift.cpp | 48 +-- .../A32/translate/impl/load_store.cpp | 53 +-- .../frontend/A32/translate/impl/misc.cpp | 15 +- .../translate/impl/status_register_access.cpp | 19 +- .../frontend/A32/translate/impl/thumb16.cpp | 28 +- ...data_processing_plain_binary_immediate.cpp | 17 +- .../impl/thumb32_load_store_dual.cpp | 3 +- .../impl/thumb32_load_store_multiple.cpp | 27 +- .../frontend/A32/translate/impl/vfp.cpp | 2 +- .../frontend/A32/translate/translate_arm.cpp | 3 +- .../A32/translate/translate_callbacks.h | 2 +- .../A32/translate/translate_thumb.cpp | 10 +- src/dynarmic/frontend/A64/a64_ir_emitter.cpp | 3 +- src/dynarmic/frontend/A64/a64_ir_emitter.h | 3 +- .../frontend/A64/a64_location_descriptor.h | 11 +- src/dynarmic/frontend/A64/a64_types.h | 5 +- src/dynarmic/frontend/A64/decoder/a64.h | 7 +- .../frontend/A64/translate/a64_translate.h | 2 +- .../frontend/A64/translate/impl/impl.cpp | 17 +- .../frontend/A64/translate/impl/simd_copy.cpp | 17 +- .../impl/simd_modified_immediate.cpp | 5 +- .../impl/simd_scalar_shift_by_immediate.cpp | 10 +- .../translate/impl/simd_scalar_three_same.cpp | 3 +- .../impl/simd_shift_by_immediate.cpp | 23 +- .../impl/simd_vector_x_indexed_element.cpp | 3 +- .../frontend/decoder/decoder_detail.h | 7 +- src/dynarmic/frontend/decoder/matcher.h | 2 +- src/dynarmic/frontend/imm.cpp | 42 +- src/dynarmic/frontend/imm.h | 24 +- src/dynarmic/ir/basic_block.cpp | 2 +- src/dynarmic/ir/basic_block.h | 7 +- src/dynarmic/ir/ir_emitter.cpp | 13 +- src/dynarmic/ir/ir_emitter.h | 3 +- src/dynarmic/ir/location_descriptor.h | 2 +- src/dynarmic/ir/microinstruction.cpp | 2 +- src/dynarmic/ir/microinstruction.h | 7 +- src/dynarmic/ir/opcodes.h | 2 +- .../ir/opt/a32_get_set_elimination_pass.cpp | 5 +- .../ir/opt/a64_get_set_elimination_pass.cpp | 3 +- .../ir/opt/a64_merge_interpret_blocks.cpp | 2 +- .../ir/opt/constant_propagation_pass.cpp | 24 +- .../ir/opt/dead_code_elimination_pass.cpp | 5 +- src/dynarmic/ir/opt/identity_removal_pass.cpp | 3 +- src/dynarmic/ir/opt/verification_pass.cpp | 5 +- src/dynarmic/ir/terminal.h | 2 +- src/dynarmic/ir/type.h | 2 +- src/dynarmic/ir/value.cpp | 11 +- src/dynarmic/ir/value.h | 5 +- tests/A32/fuzz_arm.cpp | 10 +- tests/A32/fuzz_thumb.cpp | 108 ++--- tests/A32/test_thumb_instructions.cpp | 2 +- tests/A32/testenv.h | 5 +- tests/A64/fuzz_with_unicorn.cpp | 4 +- tests/A64/testenv.h | 5 +- tests/decoder_tests.cpp | 2 +- tests/fp/FPToFixed.cpp | 2 +- tests/fp/mantissa_util_tests.cpp | 4 +- tests/fp/unpacked_tests.cpp | 2 +- tests/fuzz_util.cpp | 2 +- tests/fuzz_util.h | 2 +- tests/print_info.cpp | 6 +- tests/rsqrt_test.cpp | 2 +- tests/unicorn_emu/a32_unicorn.cpp | 9 +- tests/unicorn_emu/a32_unicorn.h | 3 +- tests/unicorn_emu/a64_unicorn.cpp | 2 +- tests/unicorn_emu/a64_unicorn.h | 3 +- 181 files changed, 987 insertions(+), 1807 deletions(-) delete mode 100644 src/dynarmic/common/assert.cpp delete mode 100644 src/dynarmic/common/assert.h delete mode 100644 src/dynarmic/common/bit_util.h delete mode 100644 src/dynarmic/common/common_types.h delete mode 100644 src/dynarmic/common/intrusive_list.h delete mode 100644 src/dynarmic/common/iterator_util.h delete mode 100644 src/dynarmic/common/macro_util.h delete mode 100644 src/dynarmic/common/scope_exit.h delete mode 100644 src/dynarmic/common/unlikely.h diff --git a/src/dynarmic/CMakeLists.txt b/src/dynarmic/CMakeLists.txt index 4c04da43..4f38b161 100644 --- a/src/dynarmic/CMakeLists.txt +++ b/src/dynarmic/CMakeLists.txt @@ -1,9 +1,5 @@ add_library(dynarmic - common/assert.cpp - common/assert.h - common/bit_util.h common/cast_util.h - common/common_types.h common/crypto/aes.cpp common/crypto/aes.h common/crypto/crc32.cpp @@ -46,18 +42,14 @@ add_library(dynarmic common/fp/unpacked.cpp common/fp/unpacked.h common/fp/util.h - common/intrusive_list.h - common/iterator_util.h common/llvm_disassemble.cpp common/llvm_disassemble.h common/lut_from_list.h - common/macro_util.h common/math_util.cpp common/math_util.h common/memory_pool.cpp common/memory_pool.h common/safe_ops.h - common/scope_exit.h common/spin_lock.h common/string_util.h common/u128.cpp diff --git a/src/dynarmic/backend/x64/a32_emit_x64.cpp b/src/dynarmic/backend/x64/a32_emit_x64.cpp index c9710540..4a3c3a35 100644 --- a/src/dynarmic/backend/x64/a32_emit_x64.cpp +++ b/src/dynarmic/backend/x64/a32_emit_x64.cpp @@ -11,6 +11,10 @@ #include #include +#include +#include +#include +#include #include "dynarmic/backend/x64/a32_jitstate.h" #include "dynarmic/backend/x64/abi.h" @@ -20,10 +24,6 @@ #include "dynarmic/backend/x64/nzcv_util.h" #include "dynarmic/backend/x64/perf_map.h" #include "dynarmic/backend/x64/stack_layout.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/common/variant_util.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" @@ -626,10 +626,10 @@ void A32EmitX64::EmitA32SetGEFlagsCompressed(A32EmitContext& ctx, IR::Inst* inst if (args[0].IsImmediate()) { const u32 imm = args[0].GetImmediateU32(); u32 ge = 0; - ge |= Common::Bit<19>(imm) ? 0xFF000000 : 0; - ge |= Common::Bit<18>(imm) ? 0x00FF0000 : 0; - ge |= Common::Bit<17>(imm) ? 0x0000FF00 : 0; - ge |= Common::Bit<16>(imm) ? 0x000000FF : 0; + ge |= mcl::bit::get_bit<19>(imm) ? 0xFF000000 : 0; + ge |= mcl::bit::get_bit<18>(imm) ? 0x00FF0000 : 0; + ge |= mcl::bit::get_bit<17>(imm) ? 0x0000FF00 : 0; + ge |= mcl::bit::get_bit<16>(imm) ? 0x000000FF : 0; code.mov(dword[r15 + offsetof(A32JitState, cpsr_ge)], ge); } else if (code.HasHostFeature(HostFeature::FastBMI2)) { @@ -689,8 +689,8 @@ void A32EmitX64::EmitA32BXWritePC(A32EmitContext& ctx, IR::Inst* inst) { if (arg.IsImmediate()) { const u32 new_pc = arg.GetImmediateU32(); - const u32 mask = Common::Bit<0>(new_pc) ? 0xFFFFFFFE : 0xFFFFFFFC; - const u32 new_upper = upper_without_t | (Common::Bit<0>(new_pc) ? 1 : 0); + const u32 mask = mcl::bit::get_bit<0>(new_pc) ? 0xFFFFFFFE : 0xFFFFFFFC; + const u32 new_upper = upper_without_t | (mcl::bit::get_bit<0>(new_pc) ? 1 : 0); code.mov(MJitStateReg(A32::Reg::PC), new_pc & mask); code.mov(dword[r15 + offsetof(A32JitState, upper_location_descriptor)], new_upper); diff --git a/src/dynarmic/backend/x64/a32_interface.cpp b/src/dynarmic/backend/x64/a32_interface.cpp index 2e7cb4e0..e066c993 100644 --- a/src/dynarmic/backend/x64/a32_interface.cpp +++ b/src/dynarmic/backend/x64/a32_interface.cpp @@ -8,6 +8,10 @@ #include #include +#include +#include +#include +#include #include "dynarmic/backend/x64/a32_emit_x64.h" #include "dynarmic/backend/x64/a32_jitstate.h" @@ -15,11 +19,7 @@ #include "dynarmic/backend/x64/callback.h" #include "dynarmic/backend/x64/devirtualize.h" #include "dynarmic/backend/x64/jitstate_info.h" -#include "dynarmic/common/assert.h" #include "dynarmic/common/atomic.h" -#include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/common/x64_disassemble.h" #include "dynarmic/frontend/A32/translate/a32_translate.h" #include "dynarmic/interface/A32/a32.h" @@ -44,10 +44,10 @@ static RunCodeCallbacks GenRunCodeCallbacks(A32::UserCallbacks* cb, CodePtr (*Lo static std::function GenRCP(const A32::UserConfig& conf) { return [conf](BlockOfCode& code) { if (conf.page_table) { - code.mov(code.r14, Common::BitCast(conf.page_table)); + code.mov(code.r14, mcl::bit_cast(conf.page_table)); } if (conf.fastmem_pointer) { - code.mov(code.r13, Common::BitCast(conf.fastmem_pointer)); + code.mov(code.r13, mcl::bit_cast(conf.fastmem_pointer)); } }; } diff --git a/src/dynarmic/backend/x64/a32_jitstate.cpp b/src/dynarmic/backend/x64/a32_jitstate.cpp index 5e70f90e..2e201c1c 100644 --- a/src/dynarmic/backend/x64/a32_jitstate.cpp +++ b/src/dynarmic/backend/x64/a32_jitstate.cpp @@ -5,11 +5,12 @@ #include "dynarmic/backend/x64/a32_jitstate.h" +#include +#include +#include + #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/nzcv_util.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" namespace Dynarmic::Backend::X64 { @@ -57,13 +58,13 @@ u32 A32JitState::Cpsr() const { // Q flag cpsr |= cpsr_q ? 1 << 27 : 0; // GE flags - cpsr |= Common::Bit<31>(cpsr_ge) ? 1 << 19 : 0; - cpsr |= Common::Bit<23>(cpsr_ge) ? 1 << 18 : 0; - cpsr |= Common::Bit<15>(cpsr_ge) ? 1 << 17 : 0; - cpsr |= Common::Bit<7>(cpsr_ge) ? 1 << 16 : 0; + cpsr |= mcl::bit::get_bit<31>(cpsr_ge) ? 1 << 19 : 0; + cpsr |= mcl::bit::get_bit<23>(cpsr_ge) ? 1 << 18 : 0; + cpsr |= mcl::bit::get_bit<15>(cpsr_ge) ? 1 << 17 : 0; + cpsr |= mcl::bit::get_bit<7>(cpsr_ge) ? 1 << 16 : 0; // E flag, T flag - cpsr |= Common::Bit<1>(upper_location_descriptor) ? 1 << 9 : 0; - cpsr |= Common::Bit<0>(upper_location_descriptor) ? 1 << 5 : 0; + cpsr |= mcl::bit::get_bit<1>(upper_location_descriptor) ? 1 << 9 : 0; + cpsr |= mcl::bit::get_bit<0>(upper_location_descriptor) ? 1 << 5 : 0; // IT state cpsr |= static_cast(upper_location_descriptor & 0b11111100'00000000); cpsr |= static_cast(upper_location_descriptor & 0b00000011'00000000) << 17; @@ -77,18 +78,18 @@ void A32JitState::SetCpsr(u32 cpsr) { // NZCV flags cpsr_nzcv = NZCV::ToX64(cpsr); // Q flag - cpsr_q = Common::Bit<27>(cpsr) ? 1 : 0; + cpsr_q = mcl::bit::get_bit<27>(cpsr) ? 1 : 0; // GE flags cpsr_ge = 0; - cpsr_ge |= Common::Bit<19>(cpsr) ? 0xFF000000 : 0; - cpsr_ge |= Common::Bit<18>(cpsr) ? 0x00FF0000 : 0; - cpsr_ge |= Common::Bit<17>(cpsr) ? 0x0000FF00 : 0; - cpsr_ge |= Common::Bit<16>(cpsr) ? 0x000000FF : 0; + cpsr_ge |= mcl::bit::get_bit<19>(cpsr) ? 0xFF000000 : 0; + cpsr_ge |= mcl::bit::get_bit<18>(cpsr) ? 0x00FF0000 : 0; + cpsr_ge |= mcl::bit::get_bit<17>(cpsr) ? 0x0000FF00 : 0; + cpsr_ge |= mcl::bit::get_bit<16>(cpsr) ? 0x000000FF : 0; upper_location_descriptor &= 0xFFFF0000; // E flag, T flag - upper_location_descriptor |= Common::Bit<9>(cpsr) ? 2 : 0; - upper_location_descriptor |= Common::Bit<5>(cpsr) ? 1 : 0; + upper_location_descriptor |= mcl::bit::get_bit<9>(cpsr) ? 2 : 0; + upper_location_descriptor |= mcl::bit::get_bit<5>(cpsr) ? 1 : 0; // IT state upper_location_descriptor |= (cpsr >> 0) & 0b11111100'00000000; upper_location_descriptor |= (cpsr >> 17) & 0b00000011'00000000; @@ -197,7 +198,7 @@ void A32JitState::SetFpscr(u32 FPSCR) { // Cumulative flags IDC, IOC, IXC, UFC, OFC, DZC fpsr_exc = FPSCR & 0x9F; - if (Common::Bit<24>(FPSCR)) { + if (mcl::bit::get_bit<24>(FPSCR)) { // VFP Flush to Zero guest_MXCSR |= (1 << 15); // SSE Flush to Zero guest_MXCSR |= (1 << 6); // SSE Denormals are Zero diff --git a/src/dynarmic/backend/x64/a32_jitstate.h b/src/dynarmic/backend/x64/a32_jitstate.h index 14cd5764..cc13abf8 100644 --- a/src/dynarmic/backend/x64/a32_jitstate.h +++ b/src/dynarmic/backend/x64/a32_jitstate.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/a64_emit_x64.cpp b/src/dynarmic/backend/x64/a64_emit_x64.cpp index 4ea4e7fc..eba49dfc 100644 --- a/src/dynarmic/backend/x64/a64_emit_x64.cpp +++ b/src/dynarmic/backend/x64/a64_emit_x64.cpp @@ -7,6 +7,9 @@ #include #include +#include +#include +#include #include #include "dynarmic/backend/x64/a64_jitstate.h" @@ -17,10 +20,6 @@ #include "dynarmic/backend/x64/nzcv_util.h" #include "dynarmic/backend/x64/perf_map.h" #include "dynarmic/backend/x64/stack_layout.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/ir/basic_block.h" diff --git a/src/dynarmic/backend/x64/a64_interface.cpp b/src/dynarmic/backend/x64/a64_interface.cpp index 8471f43b..816519d6 100644 --- a/src/dynarmic/backend/x64/a64_interface.cpp +++ b/src/dynarmic/backend/x64/a64_interface.cpp @@ -8,15 +8,16 @@ #include #include +#include +#include +#include #include "dynarmic/backend/x64/a64_emit_x64.h" #include "dynarmic/backend/x64/a64_jitstate.h" #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/devirtualize.h" #include "dynarmic/backend/x64/jitstate_info.h" -#include "dynarmic/common/assert.h" #include "dynarmic/common/atomic.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/common/x64_disassemble.h" #include "dynarmic/frontend/A64/translate/a64_translate.h" #include "dynarmic/interface/A64/a64.h" @@ -39,10 +40,10 @@ static RunCodeCallbacks GenRunCodeCallbacks(A64::UserCallbacks* cb, CodePtr (*Lo static std::function GenRCP(const A64::UserConfig& conf) { return [conf](BlockOfCode& code) { if (conf.page_table) { - code.mov(code.r14, Common::BitCast(conf.page_table)); + code.mov(code.r14, mcl::bit_cast(conf.page_table)); } if (conf.fastmem_pointer) { - code.mov(code.r13, Common::BitCast(conf.fastmem_pointer)); + code.mov(code.r13, mcl::bit_cast(conf.fastmem_pointer)); } }; } diff --git a/src/dynarmic/backend/x64/a64_jitstate.cpp b/src/dynarmic/backend/x64/a64_jitstate.cpp index c7d0e597..9f983f39 100644 --- a/src/dynarmic/backend/x64/a64_jitstate.cpp +++ b/src/dynarmic/backend/x64/a64_jitstate.cpp @@ -5,7 +5,8 @@ #include "dynarmic/backend/x64/a64_jitstate.h" -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A64/a64_location_descriptor.h" namespace Dynarmic::Backend::X64 { @@ -65,7 +66,7 @@ void A64JitState::SetFpcr(u32 value) { const std::array MXCSR_RMode{0x0, 0x4000, 0x2000, 0x6000}; guest_MXCSR |= MXCSR_RMode[(value >> 22) & 0x3]; - if (Common::Bit<24>(value)) { + if (mcl::bit::get_bit<24>(value)) { guest_MXCSR |= (1 << 15); // SSE Flush to Zero guest_MXCSR |= (1 << 6); // SSE Denormals are Zero } diff --git a/src/dynarmic/backend/x64/a64_jitstate.h b/src/dynarmic/backend/x64/a64_jitstate.h index 12479461..0929e81e 100644 --- a/src/dynarmic/backend/x64/a64_jitstate.h +++ b/src/dynarmic/backend/x64/a64_jitstate.h @@ -7,8 +7,9 @@ #include +#include + #include "dynarmic/backend/x64/nzcv_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/frontend/A64/a64_location_descriptor.h" namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/abi.cpp b/src/dynarmic/backend/x64/abi.cpp index 8535d764..d6a83b65 100644 --- a/src/dynarmic/backend/x64/abi.cpp +++ b/src/dynarmic/backend/x64/abi.cpp @@ -8,11 +8,11 @@ #include #include +#include +#include #include #include "dynarmic/backend/x64/block_of_code.h" -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/iterator_util.h" namespace Dynarmic::Backend::X64 { @@ -97,7 +97,7 @@ void ABI_PopRegistersAndAdjustStack(BlockOfCode& code, size_t frame_size, const code.add(rsp, u32(frame_info.stack_subtraction)); } - for (HostLoc gpr : Common::Reverse(regs)) { + for (HostLoc gpr : mcl::iterator::reverse(regs)) { if (HostLocIsGPR(gpr)) { code.pop(HostLocToReg64(gpr)); } diff --git a/src/dynarmic/backend/x64/abi.h b/src/dynarmic/backend/x64/abi.h index 0ccc92ba..4bddf51b 100644 --- a/src/dynarmic/backend/x64/abi.h +++ b/src/dynarmic/backend/x64/abi.h @@ -6,8 +6,9 @@ #include +#include + #include "dynarmic/backend/x64/hostloc.h" -#include "dynarmic/common/common_types.h" namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/block_of_code.cpp b/src/dynarmic/backend/x64/block_of_code.cpp index 605a9060..c0a469bf 100644 --- a/src/dynarmic/backend/x64/block_of_code.cpp +++ b/src/dynarmic/backend/x64/block_of_code.cpp @@ -15,6 +15,8 @@ #include #include +#include +#include #include #include "dynarmic/backend/x64/a32_jitstate.h" @@ -22,8 +24,6 @@ #include "dynarmic/backend/x64/hostloc.h" #include "dynarmic/backend/x64/perf_map.h" #include "dynarmic/backend/x64/stack_layout.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" namespace Dynarmic::Backend::X64 { @@ -134,8 +134,8 @@ HostFeature GetHostFeatures() { if (cpu_info.has(Cpu::tAMD)) { std::array data{}; cpu_info.getCpuid(1, data.data()); - const u32 family_base = Common::Bits<8, 11>(data[0]); - const u32 family_extended = Common::Bits<20, 27>(data[0]); + const u32 family_base = mcl::bit::get_bits<8, 11>(data[0]); + const u32 family_extended = mcl::bit::get_bits<20, 27>(data[0]); const u32 family = family_base + family_extended; if (family >= 0x19) features |= HostFeature::FastBMI2; diff --git a/src/dynarmic/backend/x64/block_of_code.h b/src/dynarmic/backend/x64/block_of_code.h index eac124b2..6e64d8c9 100644 --- a/src/dynarmic/backend/x64/block_of_code.h +++ b/src/dynarmic/backend/x64/block_of_code.h @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -19,7 +20,6 @@ #include "dynarmic/backend/x64/host_feature.h" #include "dynarmic/backend/x64/jitstate_info.h" #include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/interface/halt_reason.h" namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/block_range_information.cpp b/src/dynarmic/backend/x64/block_range_information.cpp index 7dab84e5..c590db12 100644 --- a/src/dynarmic/backend/x64/block_range_information.cpp +++ b/src/dynarmic/backend/x64/block_range_information.cpp @@ -7,10 +7,9 @@ #include #include +#include #include -#include "dynarmic/common/common_types.h" - namespace Dynarmic::Backend::X64 { template diff --git a/src/dynarmic/backend/x64/callback.h b/src/dynarmic/backend/x64/callback.h index ea7aadc0..716555da 100644 --- a/src/dynarmic/backend/x64/callback.h +++ b/src/dynarmic/backend/x64/callback.h @@ -8,10 +8,9 @@ #include #include +#include #include -#include "dynarmic/common/common_types.h" - namespace Dynarmic::Backend::X64 { using RegList = std::vector; diff --git a/src/dynarmic/backend/x64/constant_pool.cpp b/src/dynarmic/backend/x64/constant_pool.cpp index 39ffdf14..14e37f67 100644 --- a/src/dynarmic/backend/x64/constant_pool.cpp +++ b/src/dynarmic/backend/x64/constant_pool.cpp @@ -7,8 +7,9 @@ #include +#include + #include "dynarmic/backend/x64/block_of_code.h" -#include "dynarmic/common/assert.h" namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/constant_pool.h b/src/dynarmic/backend/x64/constant_pool.h index 04243993..3a5717e9 100644 --- a/src/dynarmic/backend/x64/constant_pool.h +++ b/src/dynarmic/backend/x64/constant_pool.h @@ -8,11 +8,10 @@ #include #include +#include #include #include -#include "dynarmic/common/common_types.h" - namespace Dynarmic::Backend::X64 { class BlockOfCode; diff --git a/src/dynarmic/backend/x64/constants.h b/src/dynarmic/backend/x64/constants.h index 0316cebc..13bf3696 100644 --- a/src/dynarmic/backend/x64/constants.h +++ b/src/dynarmic/backend/x64/constants.h @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/fp/rounding_mode.h" namespace Dynarmic::Backend::X64 { @@ -124,14 +125,14 @@ constexpr u32 FixupLUT(FpFixup src_qnan = FpFixup::A, FpFixup src_pos = FpFixup::A, FpFixup src_neg = FpFixup::A) { u32 fixup_lut = 0; - fixup_lut = Common::ModifyBits<0, 3, u32>(fixup_lut, static_cast(src_qnan)); - fixup_lut = Common::ModifyBits<4, 7, u32>(fixup_lut, static_cast(src_snan)); - fixup_lut = Common::ModifyBits<8, 11, u32>(fixup_lut, static_cast(src_zero)); - fixup_lut = Common::ModifyBits<12, 15, u32>(fixup_lut, static_cast(src_posone)); - fixup_lut = Common::ModifyBits<16, 19, u32>(fixup_lut, static_cast(src_neginf)); - fixup_lut = Common::ModifyBits<20, 23, u32>(fixup_lut, static_cast(src_posinf)); - fixup_lut = Common::ModifyBits<24, 27, u32>(fixup_lut, static_cast(src_pos)); - fixup_lut = Common::ModifyBits<28, 31, u32>(fixup_lut, static_cast(src_neg)); + fixup_lut = mcl::bit::set_bits<0, 3, u32>(fixup_lut, static_cast(src_qnan)); + fixup_lut = mcl::bit::set_bits<4, 7, u32>(fixup_lut, static_cast(src_snan)); + fixup_lut = mcl::bit::set_bits<8, 11, u32>(fixup_lut, static_cast(src_zero)); + fixup_lut = mcl::bit::set_bits<12, 15, u32>(fixup_lut, static_cast(src_posone)); + fixup_lut = mcl::bit::set_bits<16, 19, u32>(fixup_lut, static_cast(src_neginf)); + fixup_lut = mcl::bit::set_bits<20, 23, u32>(fixup_lut, static_cast(src_posinf)); + fixup_lut = mcl::bit::set_bits<24, 27, u32>(fixup_lut, static_cast(src_pos)); + fixup_lut = mcl::bit::set_bits<28, 31, u32>(fixup_lut, static_cast(src_neg)); return fixup_lut; } @@ -153,8 +154,8 @@ enum class FpRangeSign : u8 { // Generates 8-bit immediate LUT for vrange instruction constexpr u8 FpRangeLUT(FpRangeSelect range_select, FpRangeSign range_sign) { u8 range_lut = 0; - range_lut = Common::ModifyBits<0, 1, u8>(range_lut, static_cast(range_select)); - range_lut = Common::ModifyBits<2, 3, u8>(range_lut, static_cast(range_sign)); + range_lut = mcl::bit::set_bits<0, 1, u8>(range_lut, static_cast(range_select)); + range_lut = mcl::bit::set_bits<2, 3, u8>(range_lut, static_cast(range_sign)); return range_lut; } diff --git a/src/dynarmic/backend/x64/devirtualize.h b/src/dynarmic/backend/x64/devirtualize.h index fe124e35..778536a3 100644 --- a/src/dynarmic/backend/x64/devirtualize.h +++ b/src/dynarmic/backend/x64/devirtualize.h @@ -8,11 +8,11 @@ #include #include +#include +#include #include #include "dynarmic/backend/x64/callback.h" -#include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" namespace Dynarmic { namespace Backend::X64 { @@ -39,7 +39,7 @@ ArgCallback DevirtualizeGeneric(mcl::class_type* this_) { template ArgCallback DevirtualizeWindows(mcl::class_type* this_) { static_assert(sizeof(mfp) == 8); - return ArgCallback{Common::BitCast(mfp), reinterpret_cast(this_)}; + return ArgCallback{mcl::bit_cast(mfp), reinterpret_cast(this_)}; } template @@ -50,7 +50,7 @@ ArgCallback DevirtualizeItanium(mcl::class_type* this_) { u64 ptr; /// The required adjustment to `this`, prior to the call. u64 adj; - } mfp_struct = Common::BitCast(mfp); + } mfp_struct = mcl::bit_cast(mfp); static_assert(sizeof(MemberFunctionPointer) == 16); static_assert(sizeof(MemberFunctionPointer) == sizeof(mfp)); @@ -58,8 +58,8 @@ ArgCallback DevirtualizeItanium(mcl::class_type* this_) { u64 fn_ptr = mfp_struct.ptr; u64 this_ptr = reinterpret_cast(this_) + mfp_struct.adj; if (mfp_struct.ptr & 1) { - u64 vtable = Common::BitCastPointee(this_ptr); - fn_ptr = Common::BitCastPointee(vtable + fn_ptr - 1); + u64 vtable = mcl::bit_cast_pointee(this_ptr); + fn_ptr = mcl::bit_cast_pointee(vtable + fn_ptr - 1); } return ArgCallback{fn_ptr, this_ptr}; } diff --git a/src/dynarmic/backend/x64/emit_x64.cpp b/src/dynarmic/backend/x64/emit_x64.cpp index 3a71842f..eb8196a0 100644 --- a/src/dynarmic/backend/x64/emit_x64.cpp +++ b/src/dynarmic/backend/x64/emit_x64.cpp @@ -7,16 +7,16 @@ #include +#include +#include +#include +#include #include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/nzcv_util.h" #include "dynarmic/backend/x64/perf_map.h" #include "dynarmic/backend/x64/stack_layout.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/common/variant_util.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" @@ -164,10 +164,10 @@ void EmitX64::EmitNZCVFromPackedFlags(EmitContext& ctx, IR::Inst* inst) { if (args[0].IsImmediate()) { const Xbyak::Reg32 nzcv = ctx.reg_alloc.ScratchGpr().cvt32(); u32 value = 0; - value |= Common::Bit<31>(args[0].GetImmediateU32()) ? (1 << 15) : 0; - value |= Common::Bit<30>(args[0].GetImmediateU32()) ? (1 << 14) : 0; - value |= Common::Bit<29>(args[0].GetImmediateU32()) ? (1 << 8) : 0; - value |= Common::Bit<28>(args[0].GetImmediateU32()) ? (1 << 0) : 0; + value |= mcl::bit::get_bit<31>(args[0].GetImmediateU32()) ? (1 << 15) : 0; + value |= mcl::bit::get_bit<30>(args[0].GetImmediateU32()) ? (1 << 14) : 0; + value |= mcl::bit::get_bit<29>(args[0].GetImmediateU32()) ? (1 << 8) : 0; + value |= mcl::bit::get_bit<28>(args[0].GetImmediateU32()) ? (1 << 0) : 0; code.mov(nzcv, value); ctx.reg_alloc.DefineValue(inst, nzcv); } else if (code.HasHostFeature(HostFeature::FastBMI2)) { @@ -204,44 +204,44 @@ Xbyak::Label EmitX64::EmitCond(IR::Cond cond) { // add al, 0x7F restores OF switch (cond) { - case IR::Cond::EQ: //z + case IR::Cond::EQ: // z code.sahf(); code.jz(pass); break; - case IR::Cond::NE: //!z + case IR::Cond::NE: //! z code.sahf(); code.jnz(pass); break; - case IR::Cond::CS: //c + case IR::Cond::CS: // c code.sahf(); code.jc(pass); break; - case IR::Cond::CC: //!c + case IR::Cond::CC: //! c code.sahf(); code.jnc(pass); break; - case IR::Cond::MI: //n + case IR::Cond::MI: // n code.sahf(); code.js(pass); break; - case IR::Cond::PL: //!n + case IR::Cond::PL: //! n code.sahf(); code.jns(pass); break; - case IR::Cond::VS: //v + case IR::Cond::VS: // v code.cmp(al, 0x81); code.jo(pass); break; - case IR::Cond::VC: //!v + case IR::Cond::VC: //! v code.cmp(al, 0x81); code.jno(pass); break; - case IR::Cond::HI: //c & !z + case IR::Cond::HI: // c & !z code.sahf(); code.cmc(); code.ja(pass); break; - case IR::Cond::LS: //!c | z + case IR::Cond::LS: //! c | z code.sahf(); code.cmc(); code.jna(pass); diff --git a/src/dynarmic/backend/x64/emit_x64.h b/src/dynarmic/backend/x64/emit_x64.h index 5290da15..08a84640 100644 --- a/src/dynarmic/backend/x64/emit_x64.h +++ b/src/dynarmic/backend/x64/emit_x64.h @@ -11,13 +11,13 @@ #include #include +#include #include #include #include #include "dynarmic/backend/x64/exception_handler.h" #include "dynarmic/backend/x64/reg_alloc.h" -#include "dynarmic/common/bit_util.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/ir/location_descriptor.h" #include "dynarmic/ir/terminal.h" @@ -41,10 +41,10 @@ using A64FullVectorWidth = std::integral_constant; // relative to the size of a vector register. e.g. T = u32 would result // in a std::array. template -using VectorArray = std::array()>; +using VectorArray = std::array>; template -using HalfVectorArray = std::array() / 2>; +using HalfVectorArray = std::array / 2>; struct EmitContext { EmitContext(RegAlloc& reg_alloc, IR::Block& block); diff --git a/src/dynarmic/backend/x64/emit_x64_aes.cpp b/src/dynarmic/backend/x64/emit_x64_aes.cpp index be9faa3e..9430f072 100644 --- a/src/dynarmic/backend/x64/emit_x64_aes.cpp +++ b/src/dynarmic/backend/x64/emit_x64_aes.cpp @@ -3,10 +3,11 @@ * SPDX-License-Identifier: 0BSD */ +#include + #include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/crypto/aes.h" #include "dynarmic/ir/microinstruction.h" diff --git a/src/dynarmic/backend/x64/emit_x64_data_processing.cpp b/src/dynarmic/backend/x64/emit_x64_data_processing.cpp index c79d342d..eead879a 100644 --- a/src/dynarmic/backend/x64/emit_x64_data_processing.cpp +++ b/src/dynarmic/backend/x64/emit_x64_data_processing.cpp @@ -6,10 +6,11 @@ #include #include +#include +#include + #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" @@ -146,44 +147,44 @@ static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst* // add al, 0x7F restores OF switch (args[0].GetImmediateCond()) { - case IR::Cond::EQ: //z + case IR::Cond::EQ: // z code.sahf(); code.cmovz(else_, then_); break; - case IR::Cond::NE: //!z + case IR::Cond::NE: //! z code.sahf(); code.cmovnz(else_, then_); break; - case IR::Cond::CS: //c + case IR::Cond::CS: // c code.sahf(); code.cmovc(else_, then_); break; - case IR::Cond::CC: //!c + case IR::Cond::CC: //! c code.sahf(); code.cmovnc(else_, then_); break; - case IR::Cond::MI: //n + case IR::Cond::MI: // n code.sahf(); code.cmovs(else_, then_); break; - case IR::Cond::PL: //!n + case IR::Cond::PL: //! n code.sahf(); code.cmovns(else_, then_); break; - case IR::Cond::VS: //v + case IR::Cond::VS: // v code.cmp(nzcv.cvt8(), 0x81); code.cmovo(else_, then_); break; - case IR::Cond::VC: //!v + case IR::Cond::VC: //! v code.cmp(nzcv.cvt8(), 0x81); code.cmovno(else_, then_); break; - case IR::Cond::HI: //c & !z + case IR::Cond::HI: // c & !z code.sahf(); code.cmc(); code.cmova(else_, then_); break; - case IR::Cond::LS: //!c | z + case IR::Cond::LS: //! c | z code.sahf(); code.cmc(); code.cmovna(else_, then_); diff --git a/src/dynarmic/backend/x64/emit_x64_floating_point.cpp b/src/dynarmic/backend/x64/emit_x64_floating_point.cpp index 1806e895..30a8c301 100644 --- a/src/dynarmic/backend/x64/emit_x64_floating_point.cpp +++ b/src/dynarmic/backend/x64/emit_x64_floating_point.cpp @@ -7,20 +7,20 @@ #include #include +#include #include #include #include #include #include +#include #include #include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/constants.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/assert.h" #include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" diff --git a/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc b/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc index 02ec0095..b82aabb1 100644 --- a/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc +++ b/src/dynarmic/backend/x64/emit_x64_memory.cpp.inc @@ -3,7 +3,7 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/macro_util.h" +#include #define AxxEmitX64 CONCATENATE_TOKENS(Axx, EmitX64) #define AxxEmitContext CONCATENATE_TOKENS(Axx, EmitContext) @@ -98,10 +98,10 @@ void AxxEmitX64::EmitMemoryRead(AxxEmitContext& ctx, IR::Inst* inst) { const auto location = EmitReadMemoryMov(code, value_idx, src_ptr, ordered); fastmem_patch_info.emplace( - Common::BitCast(location), + mcl::bit_cast(location), FastmemPatchInfo{ - Common::BitCast(code.getCurr()), - Common::BitCast(wrapped_fn), + mcl::bit_cast(code.getCurr()), + mcl::bit_cast(wrapped_fn), *fastmem_marker, conf.recompile_on_fastmem_failure, }); @@ -178,10 +178,10 @@ void AxxEmitX64::EmitMemoryWrite(AxxEmitContext& ctx, IR::Inst* inst) { const auto location = EmitWriteMemoryMov(code, dest_ptr, value_idx, ordered); fastmem_patch_info.emplace( - Common::BitCast(location), + mcl::bit_cast(location), FastmemPatchInfo{ - Common::BitCast(code.getCurr()), - Common::BitCast(wrapped_fn), + mcl::bit_cast(code.getCurr()), + mcl::bit_cast(wrapped_fn), *fastmem_marker, conf.recompile_on_fastmem_failure, }); @@ -339,7 +339,7 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in EmitExclusiveLock(code, conf, tmp, tmp2.cvt32()); code.mov(code.byte[r15 + offsetof(AxxJitState, exclusive_state)], u8(1)); - code.mov(tmp, Common::BitCast(GetExclusiveMonitorAddressPointer(conf.global_monitor, conf.processor_id))); + code.mov(tmp, mcl::bit_cast(GetExclusiveMonitorAddressPointer(conf.global_monitor, conf.processor_id))); code.mov(qword[tmp], vaddr); const auto fastmem_marker = ShouldFastmem(ctx, inst); @@ -352,10 +352,10 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in const auto location = EmitReadMemoryMov(code, value_idx, src_ptr, ordered); fastmem_patch_info.emplace( - Common::BitCast(location), + mcl::bit_cast(location), FastmemPatchInfo{ - Common::BitCast(code.getCurr()), - Common::BitCast(wrapped_fn), + mcl::bit_cast(code.getCurr()), + mcl::bit_cast(wrapped_fn), *fastmem_marker, conf.recompile_on_exclusive_fastmem_failure, }); @@ -373,7 +373,7 @@ void AxxEmitX64::EmitExclusiveReadMemoryInline(AxxEmitContext& ctx, IR::Inst* in code.call(wrapped_fn); } - code.mov(tmp, Common::BitCast(GetExclusiveMonitorValuePointer(conf.global_monitor, conf.processor_id))); + code.mov(tmp, mcl::bit_cast(GetExclusiveMonitorValuePointer(conf.global_monitor, conf.processor_id))); EmitWriteMemoryMov(code, tmp, value_idx, false); EmitExclusiveUnlock(code, conf, tmp, tmp2.cvt32()); @@ -418,7 +418,7 @@ void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* i Xbyak::Label end; - code.mov(tmp, Common::BitCast(GetExclusiveMonitorAddressPointer(conf.global_monitor, conf.processor_id))); + code.mov(tmp, mcl::bit_cast(GetExclusiveMonitorAddressPointer(conf.global_monitor, conf.processor_id))); code.mov(status, u32(1)); code.cmp(code.byte[r15 + offsetof(AxxJitState, exclusive_state)], u8(0)); code.je(end, code.T_NEAR); @@ -428,7 +428,7 @@ void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* i EmitExclusiveTestAndClear(code, conf, vaddr, tmp, rax); code.mov(code.byte[r15 + offsetof(AxxJitState, exclusive_state)], u8(0)); - code.mov(tmp, Common::BitCast(GetExclusiveMonitorValuePointer(conf.global_monitor, conf.processor_id))); + code.mov(tmp, mcl::bit_cast(GetExclusiveMonitorValuePointer(conf.global_monitor, conf.processor_id))); if constexpr (bitsize == 128) { code.mov(rax, qword[tmp + 0]); @@ -488,10 +488,10 @@ void AxxEmitX64::EmitExclusiveWriteMemoryInline(AxxEmitContext& ctx, IR::Inst* i code.call(wrapped_fn); fastmem_patch_info.emplace( - Common::BitCast(location), + mcl::bit_cast(location), FastmemPatchInfo{ - Common::BitCast(code.getCurr()), - Common::BitCast(wrapped_fn), + mcl::bit_cast(code.getCurr()), + mcl::bit_cast(wrapped_fn), *fastmem_marker, conf.recompile_on_exclusive_fastmem_failure, }); diff --git a/src/dynarmic/backend/x64/emit_x64_memory.h b/src/dynarmic/backend/x64/emit_x64_memory.h index e92ed729..29146820 100644 --- a/src/dynarmic/backend/x64/emit_x64_memory.h +++ b/src/dynarmic/backend/x64/emit_x64_memory.h @@ -3,6 +3,7 @@ * SPDX-License-Identifier: 0BSD */ +#include #include #include "dynarmic/backend/x64/a32_emit_x64.h" @@ -343,7 +344,7 @@ void EmitExclusiveLock(BlockOfCode& code, const UserConfig& conf, Xbyak::Reg64 p return; } - code.mov(pointer, Common::BitCast(GetExclusiveMonitorLockPointer(conf.global_monitor))); + code.mov(pointer, mcl::bit_cast(GetExclusiveMonitorLockPointer(conf.global_monitor))); EmitSpinLockLock(code, pointer, tmp); } @@ -353,7 +354,7 @@ void EmitExclusiveUnlock(BlockOfCode& code, const UserConfig& conf, Xbyak::Reg64 return; } - code.mov(pointer, Common::BitCast(GetExclusiveMonitorLockPointer(conf.global_monitor))); + code.mov(pointer, mcl::bit_cast(GetExclusiveMonitorLockPointer(conf.global_monitor))); EmitSpinLockUnlock(code, pointer, tmp); } @@ -370,7 +371,7 @@ void EmitExclusiveTestAndClear(BlockOfCode& code, const UserConfig& conf, Xbyak: continue; } Xbyak::Label ok; - code.mov(pointer, Common::BitCast(GetExclusiveMonitorAddressPointer(conf.global_monitor, processor_index))); + code.mov(pointer, mcl::bit_cast(GetExclusiveMonitorAddressPointer(conf.global_monitor, processor_index))); code.cmp(qword[pointer], vaddr); code.jne(ok); code.mov(qword[pointer], tmp); diff --git a/src/dynarmic/backend/x64/emit_x64_saturation.cpp b/src/dynarmic/backend/x64/emit_x64_saturation.cpp index 35e99fd9..7301c77b 100644 --- a/src/dynarmic/backend/x64/emit_x64_saturation.cpp +++ b/src/dynarmic/backend/x64/emit_x64_saturation.cpp @@ -5,13 +5,13 @@ #include +#include +#include +#include #include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" diff --git a/src/dynarmic/backend/x64/emit_x64_vector.cpp b/src/dynarmic/backend/x64/emit_x64_vector.cpp index e8e9e6df..38e0e672 100644 --- a/src/dynarmic/backend/x64/emit_x64_vector.cpp +++ b/src/dynarmic/backend/x64/emit_x64_vector.cpp @@ -8,6 +8,11 @@ #include #include +#include +#include +#include +#include +#include #include #include @@ -15,9 +20,6 @@ #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/constants.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/math_util.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" @@ -529,7 +531,7 @@ void EmitX64::EmitVectorArithmeticShiftRight64(EmitContext& ctx, IR::Inst* inst) template static constexpr T VShift(T x, T y) { const s8 shift_amount = static_cast(static_cast(y)); - const s64 bit_size = static_cast(Common::BitSize()); + const s64 bit_size = static_cast(mcl::bitsizeof); if constexpr (std::is_signed_v) { if (shift_amount >= bit_size) { @@ -859,10 +861,10 @@ void EmitX64::EmitVectorBroadcastElement16(EmitContext& ctx, IR::Inst* inst) { } if (index < 4) { - code.pshuflw(a, a, Common::Replicate(index, 2)); + code.pshuflw(a, a, mcl::bit::replicate_element<2, u8>(index)); code.punpcklqdq(a, a); } else { - code.pshufhw(a, a, Common::Replicate(u8(index - 4), 2)); + code.pshufhw(a, a, mcl::bit::replicate_element<2, u8>(u8(index - 4))); code.punpckhqdq(a, a); } @@ -876,7 +878,7 @@ void EmitX64::EmitVectorBroadcastElement32(EmitContext& ctx, IR::Inst* inst) { const u8 index = args[1].GetImmediateU8(); ASSERT(index < 4); - code.pshufd(a, a, Common::Replicate(index, 2)); + code.pshufd(a, a, mcl::bit::replicate_element<2, u8>(index)); ctx.reg_alloc.DefineValue(inst, a); } @@ -889,7 +891,7 @@ void EmitX64::EmitVectorBroadcastElement64(EmitContext& ctx, IR::Inst* inst) { ASSERT(index < 2); if (code.HasHostFeature(HostFeature::AVX)) { - code.vpermilpd(a, a, Common::Replicate(index, 1)); + code.vpermilpd(a, a, mcl::bit::replicate_element<1, u8>(index)); } else { if (index == 0) { code.punpcklqdq(a, a); @@ -905,7 +907,7 @@ static void EmitVectorCountLeadingZeros(VectorArray& result, const VectorArra for (size_t i = 0; i < result.size(); i++) { T element = data[i]; - size_t count = Common::BitSize(); + size_t count = mcl::bitsizeof; while (element != 0) { element >>= 1; --count; @@ -1636,7 +1638,7 @@ void EmitX64::EmitVectorLogicalShiftLeft8(EmitContext& ctx, IR::Inst* inst) { code.gf2p8affineqb(result, code.MConst(xword, shift_matrix, shift_matrix), 0); } else { const u64 replicand = (0xFFULL << shift_amount) & 0xFF; - const u64 mask = Common::Replicate(replicand, Common::BitSize()); + const u64 mask = mcl::bit::replicate_element(replicand); code.psllw(result, shift_amount); code.pand(result, code.MConst(xword, mask, mask)); @@ -1693,7 +1695,7 @@ void EmitX64::EmitVectorLogicalShiftRight8(EmitContext& ctx, IR::Inst* inst) { code.gf2p8affineqb(result, code.MConst(xword, shift_matrix, shift_matrix), 0); } else { const u64 replicand = 0xFEULL >> shift_amount; - const u64 mask = Common::Replicate(replicand, Common::BitSize()); + const u64 mask = mcl::bit::replicate_element(replicand); code.psrlw(result, shift_amount); code.pand(result, code.MConst(xword, mask, mask)); @@ -2775,7 +2777,7 @@ void EmitX64::EmitVectorPairedMinU32(EmitContext& ctx, IR::Inst* inst) { template static D PolynomialMultiply(T lhs, T rhs) { - constexpr size_t bit_size = Common::BitSize(); + constexpr size_t bit_size = mcl::bitsizeof; const std::bitset operand(lhs); D res = 0; @@ -2890,11 +2892,11 @@ void EmitX64::EmitVectorPolynomialMultiplyLong64(EmitContext& ctx, IR::Inst* ins EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& a, const VectorArray& b) { const auto handle_high_bits = [](u64 lhs, u64 rhs) { - constexpr size_t bit_size = Common::BitSize(); + constexpr size_t bit_size = mcl::bitsizeof; u64 result = 0; for (size_t i = 1; i < bit_size; i++) { - if (Common::Bit(i, lhs)) { + if (mcl::bit::get_bit(i, lhs)) { result ^= rhs >> (bit_size - i); } } @@ -2945,7 +2947,7 @@ void EmitX64::EmitVectorPopulationCount(EmitContext& ctx, IR::Inst* inst) { EmitOneArgumentFallback(code, ctx, inst, [](VectorArray& result, const VectorArray& a) { std::transform(a.begin(), a.end(), result.begin(), [](u8 val) { - return static_cast(Common::BitCount(val)); + return static_cast(mcl::bit::count_ones(val)); }); }); } @@ -3194,10 +3196,10 @@ static void RoundingShiftLeft(VectorArray& out, const VectorArray& lhs, co using signed_type = std::make_signed_t; using unsigned_type = std::make_unsigned_t; - constexpr auto bit_size = static_cast(Common::BitSize()); + constexpr auto bit_size = static_cast(mcl::bitsizeof); for (size_t i = 0; i < out.size(); i++) { - const s64 extended_shift = Common::SignExtend<8>(rhs[i] & 0xFF); + const s64 extended_shift = static_cast(mcl::bit::sign_extend<8, u64>(rhs[i] & 0xFF)); if (extended_shift >= 0) { if (extended_shift >= bit_size) { @@ -4290,7 +4292,7 @@ static bool VectorSignedSaturatedShiftLeft(VectorArray& dst, const VectorArra bool qc_flag = false; - constexpr size_t bit_size_minus_one = Common::BitSize() - 1; + constexpr size_t bit_size_minus_one = mcl::bitsizeof - 1; const auto saturate = [bit_size_minus_one](T value) { return static_cast((static_cast(value) >> bit_size_minus_one) + (U{1} << bit_size_minus_one) - 1); @@ -4298,7 +4300,7 @@ static bool VectorSignedSaturatedShiftLeft(VectorArray& dst, const VectorArra for (size_t i = 0; i < dst.size(); i++) { const T element = data[i]; - const T shift = std::clamp(static_cast(Common::SignExtend<8>(shift_values[i] & 0xFF)), + const T shift = std::clamp(static_cast(mcl::bit::sign_extend<8>(static_cast(shift_values[i] & 0xFF))), -static_cast(bit_size_minus_one), std::numeric_limits::max()); if (element == 0) { @@ -4346,12 +4348,12 @@ template> static bool VectorSignedSaturatedShiftLeftUnsigned(VectorArray& dst, const VectorArray& data, const VectorArray& shift_values) { static_assert(std::is_signed_v, "T must be signed."); - constexpr size_t bit_size_minus_one = Common::BitSize() - 1; + constexpr size_t bit_size_minus_one = mcl::bitsizeof - 1; bool qc_flag = false; for (size_t i = 0; i < dst.size(); i++) { const T element = data[i]; - const T shift = std::clamp(static_cast(Common::SignExtend<8>(shift_values[i] & 0xFF)), + const T shift = std::clamp(static_cast(mcl::bit::sign_extend<8>(static_cast(shift_values[i] & 0xFF))), -static_cast(bit_size_minus_one), std::numeric_limits::max()); if (element == 0) { @@ -4709,7 +4711,7 @@ void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) { for (size_t i = 0; i < table_size; ++i) { const Xbyak::Xmm xmm_table = ctx.reg_alloc.UseScratchXmm(table[i]); const Xbyak::Opmask table_mask = k1; - const u64 table_index = Common::Replicate(i * 16, 8); + const u64 table_index = mcl::bit::replicate_element(i * 16); code.vpcmpeqb(table_mask, masked, code.MConst(xword, table_index, table_index)); @@ -4737,7 +4739,7 @@ void EmitX64::EmitVectorTableLookup128(EmitContext& ctx, IR::Inst* inst) { for (size_t i = 0; i < table_size; ++i) { const Xbyak::Xmm xmm_table = ctx.reg_alloc.UseScratchXmm(table[i]); - const u64 table_index = Common::Replicate(i * 16, 8); + const u64 table_index = mcl::bit::replicate_element(i * 16); if (table_index == 0) { code.pxor(xmm0, xmm0); @@ -5044,7 +5046,7 @@ void EmitX64::EmitVectorUnsignedRecipEstimate(EmitContext& ctx, IR::Inst* inst) continue; } - const u32 input = Common::Bits<23, 31>(a[i]); + const u32 input = mcl::bit::get_bits<23, 31>(a[i]); const u32 estimate = Common::RecipEstimate(input); result[i] = (0b100000000 | estimate) << 23; @@ -5060,7 +5062,7 @@ void EmitX64::EmitVectorUnsignedRecipSqrtEstimate(EmitContext& ctx, IR::Inst* in continue; } - const u32 input = Common::Bits<23, 31>(a[i]); + const u32 input = mcl::bit::get_bits<23, 31>(a[i]); const u32 estimate = Common::RecipSqrtEstimate(input); result[i] = (0b100000000 | estimate) << 23; @@ -5073,7 +5075,7 @@ void EmitX64::EmitVectorUnsignedRecipSqrtEstimate(EmitContext& ctx, IR::Inst* in template> static bool EmitVectorUnsignedSaturatedAccumulateSigned(VectorArray& result, const VectorArray& lhs, const VectorArray& rhs) { static_assert(std::is_signed_v, "T must be signed."); - static_assert(Common::BitSize() < 64, "T must be less than 64 bits in size."); + static_assert(mcl::bitsizeof < 64, "T must be less than 64 bits in size."); bool qc_flag = false; @@ -5177,12 +5179,12 @@ static bool VectorUnsignedSaturatedShiftLeft(VectorArray& dst, const VectorAr bool qc_flag = false; - constexpr size_t bit_size = Common::BitSize(); + constexpr size_t bit_size = mcl::bitsizeof; constexpr S negative_bit_size = -static_cast(bit_size); for (size_t i = 0; i < dst.size(); i++) { const T element = data[i]; - const S shift = std::clamp(static_cast(Common::SignExtend<8>(shift_values[i] & 0xFF)), + const S shift = std::clamp(static_cast(mcl::bit::sign_extend<8>(static_cast(shift_values[i] & 0xFF))), negative_bit_size, std::numeric_limits::max()); if (element == 0 || shift <= negative_bit_size) { diff --git a/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp b/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp index ac1c7e57..d3275cb5 100644 --- a/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp +++ b/src/dynarmic/backend/x64/emit_x64_vector_floating_point.cpp @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -21,7 +22,6 @@ #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/constants.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/assert.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/op.h" @@ -562,7 +562,7 @@ template void FPVectorAbs(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { using FPT = mcl::unsigned_integer_of_size; constexpr FPT non_sign_mask = FP::FPInfo::sign_mask - FPT(1u); - constexpr u64 non_sign_mask64 = Common::Replicate(non_sign_mask, fsize); + constexpr u64 non_sign_mask64 = mcl::bit::replicate_element(non_sign_mask); auto args = ctx.reg_alloc.GetArgumentInfo(inst); @@ -1229,7 +1229,7 @@ template void FPVectorNeg(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) { using FPT = mcl::unsigned_integer_of_size; constexpr FPT sign_mask = FP::FPInfo::sign_mask; - constexpr u64 sign_mask64 = Common::Replicate(sign_mask, fsize); + constexpr u64 sign_mask64 = mcl::bit::replicate_element(sign_mask); auto args = ctx.reg_alloc.GetArgumentInfo(inst); diff --git a/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp b/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp index 628b667e..8ebf1610 100644 --- a/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp +++ b/src/dynarmic/backend/x64/emit_x64_vector_saturation.cpp @@ -3,10 +3,11 @@ * SPDX-License-Identifier: 0BSD */ +#include + #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/constants.h" #include "dynarmic/backend/x64/emit_x64.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" diff --git a/src/dynarmic/backend/x64/exception_handler.h b/src/dynarmic/backend/x64/exception_handler.h index 0e361ced..0e094eba 100644 --- a/src/dynarmic/backend/x64/exception_handler.h +++ b/src/dynarmic/backend/x64/exception_handler.h @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/exception_handler_macos.cpp b/src/dynarmic/backend/x64/exception_handler_macos.cpp index 53bc8abc..fbec78b1 100644 --- a/src/dynarmic/backend/x64/exception_handler_macos.cpp +++ b/src/dynarmic/backend/x64/exception_handler_macos.cpp @@ -14,12 +14,12 @@ #include #include +#include +#include +#include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/exception_handler.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" #define mig_external extern "C" #include "dynarmic/backend/x64/mig/mach_exc_server.h" @@ -120,7 +120,7 @@ kern_return_t MachHandler::HandleRequest(x86_thread_state64_t* ts) { FakeCall fc = iter->cb(ts->__rip); ts->__rsp -= sizeof(u64); - *Common::BitCast(ts->__rsp) = fc.ret_rip; + *mcl::bit_cast(ts->__rsp) = fc.ret_rip; ts->__rip = fc.call_rip; return KERN_SUCCESS; @@ -189,7 +189,7 @@ mig_external kern_return_t catch_mach_exception_raise_state( struct ExceptionHandler::Impl final { Impl(BlockOfCode& code) - : code_begin(Common::BitCast(code.getCode())) + : code_begin(mcl::bit_cast(code.getCode())) , code_end(code_begin + code.GetTotalCodeSize()) {} void SetCallback(std::function cb) { diff --git a/src/dynarmic/backend/x64/exception_handler_posix.cpp b/src/dynarmic/backend/x64/exception_handler_posix.cpp index bdaac0c3..3a997d95 100644 --- a/src/dynarmic/backend/x64/exception_handler_posix.cpp +++ b/src/dynarmic/backend/x64/exception_handler_posix.cpp @@ -19,10 +19,11 @@ #include #include +#include +#include +#include + #include "dynarmic/backend/x64/block_of_code.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" namespace Dynarmic::Backend::X64 { @@ -142,7 +143,7 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { FakeCall fc = iter->cb(CTX_RIP); CTX_RSP -= sizeof(u64); - *Common::BitCast(CTX_RSP) = fc.ret_rip; + *mcl::bit_cast(CTX_RSP) = fc.ret_rip; CTX_RIP = fc.call_rip; return; @@ -170,7 +171,7 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) { struct ExceptionHandler::Impl final { Impl(BlockOfCode& code) - : code_begin(Common::BitCast(code.getCode())) + : code_begin(mcl::bit_cast(code.getCode())) , code_end(code_begin + code.GetTotalCodeSize()) {} void SetCallback(std::function cb) { diff --git a/src/dynarmic/backend/x64/exception_handler_windows.cpp b/src/dynarmic/backend/x64/exception_handler_windows.cpp index cb746eb2..82479b9c 100644 --- a/src/dynarmic/backend/x64/exception_handler_windows.cpp +++ b/src/dynarmic/backend/x64/exception_handler_windows.cpp @@ -9,11 +9,12 @@ #include #include +#include +#include +#include + #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/exception_handler.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/safe_ops.h" using UBYTE = u8; @@ -178,20 +179,20 @@ struct ExceptionHandler::Impl final { // Our 3rd argument is a PCONTEXT. // If not within our codeblock, ignore this exception. - code.mov(code.rax, Safe::Negate(Common::BitCast(code.getCode()))); + code.mov(code.rax, Safe::Negate(mcl::bit_cast(code.getCode()))); code.add(code.rax, code.qword[code.ABI_PARAM3 + Xbyak::RegExp(offsetof(CONTEXT, Rip))]); code.cmp(code.rax, static_cast(code.GetTotalCodeSize())); code.ja(exception_handler_without_cb); code.sub(code.rsp, 8); - code.mov(code.ABI_PARAM1, Common::BitCast(&cb)); + code.mov(code.ABI_PARAM1, mcl::bit_cast(&cb)); code.mov(code.ABI_PARAM2, code.ABI_PARAM3); code.CallLambda( [](const std::function& cb_, PCONTEXT ctx) { FakeCall fc = cb_(ctx->Rip); ctx->Rsp -= sizeof(u64); - *Common::BitCast(ctx->Rsp) = fc.ret_rip; + *mcl::bit_cast(ctx->Rsp) = fc.ret_rip; ctx->Rip = fc.call_rip; }); code.add(code.rsp, 8); diff --git a/src/dynarmic/backend/x64/exclusive_monitor.cpp b/src/dynarmic/backend/x64/exclusive_monitor.cpp index 6a323b9f..68ce912c 100644 --- a/src/dynarmic/backend/x64/exclusive_monitor.cpp +++ b/src/dynarmic/backend/x64/exclusive_monitor.cpp @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include namespace Dynarmic { diff --git a/src/dynarmic/backend/x64/host_feature.h b/src/dynarmic/backend/x64/host_feature.h index baf96a66..8e3b14c7 100644 --- a/src/dynarmic/backend/x64/host_feature.h +++ b/src/dynarmic/backend/x64/host_feature.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/hostloc.h b/src/dynarmic/backend/x64/hostloc.h index b6be1146..dbf526b7 100644 --- a/src/dynarmic/backend/x64/hostloc.h +++ b/src/dynarmic/backend/x64/hostloc.h @@ -4,11 +4,10 @@ */ #pragma once +#include +#include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" - namespace Dynarmic::Backend::X64 { enum class HostLoc { diff --git a/src/dynarmic/backend/x64/nzcv_util.h b/src/dynarmic/backend/x64/nzcv_util.h index 389723a8..3a70cf4f 100644 --- a/src/dynarmic/backend/x64/nzcv_util.h +++ b/src/dynarmic/backend/x64/nzcv_util.h @@ -5,8 +5,7 @@ #pragma once -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64::NZCV { @@ -29,10 +28,10 @@ constexpr u32 from_x64_multiplier = 0x1021'0000; inline u32 ToX64(u32 nzcv) { /* Naive implementation: u32 x64_flags = 0; - x64_flags |= Common::Bit<31>(cpsr) ? 1 << 15 : 0; - x64_flags |= Common::Bit<30>(cpsr) ? 1 << 14 : 0; - x64_flags |= Common::Bit<29>(cpsr) ? 1 << 8 : 0; - x64_flags |= Common::Bit<28>(cpsr) ? 1 : 0; + x64_flags |= mcl::bit::get_bit<31>(cpsr) ? 1 << 15 : 0; + x64_flags |= mcl::bit::get_bit<30>(cpsr) ? 1 << 14 : 0; + x64_flags |= mcl::bit::get_bit<29>(cpsr) ? 1 << 8 : 0; + x64_flags |= mcl::bit::get_bit<28>(cpsr) ? 1 : 0; return x64_flags; */ return ((nzcv >> 28) * to_x64_multiplier) & x64_mask; @@ -41,10 +40,10 @@ inline u32 ToX64(u32 nzcv) { inline u32 FromX64(u32 x64_flags) { /* Naive implementation: u32 nzcv = 0; - nzcv |= Common::Bit<15>(x64_flags) ? 1 << 31 : 0; - nzcv |= Common::Bit<14>(x64_flags) ? 1 << 30 : 0; - nzcv |= Common::Bit<8>(x64_flags) ? 1 << 29 : 0; - nzcv |= Common::Bit<0>(x64_flags) ? 1 << 28 : 0; + nzcv |= mcl::bit::get_bit<15>(x64_flags) ? 1 << 31 : 0; + nzcv |= mcl::bit::get_bit<14>(x64_flags) ? 1 << 30 : 0; + nzcv |= mcl::bit::get_bit<8>(x64_flags) ? 1 << 29 : 0; + nzcv |= mcl::bit::get_bit<0>(x64_flags) ? 1 << 28 : 0; return nzcv; */ return ((x64_flags & x64_mask) * from_x64_multiplier) & arm_mask; diff --git a/src/dynarmic/backend/x64/oparg.h b/src/dynarmic/backend/x64/oparg.h index d35297b9..70c60dfb 100644 --- a/src/dynarmic/backend/x64/oparg.h +++ b/src/dynarmic/backend/x64/oparg.h @@ -5,10 +5,9 @@ #pragma once +#include #include -#include "dynarmic/common/assert.h" - namespace Dynarmic::Backend::X64 { struct OpArg { diff --git a/src/dynarmic/backend/x64/perf_map.cpp b/src/dynarmic/backend/x64/perf_map.cpp index 4a74081f..88691dbf 100644 --- a/src/dynarmic/backend/x64/perf_map.cpp +++ b/src/dynarmic/backend/x64/perf_map.cpp @@ -15,11 +15,10 @@ # include # include +# include # include # include -# include "dynarmic/common/common_types.h" - namespace Dynarmic::Backend::X64 { namespace { diff --git a/src/dynarmic/backend/x64/perf_map.h b/src/dynarmic/backend/x64/perf_map.h index 02cd0b85..7d739ae6 100644 --- a/src/dynarmic/backend/x64/perf_map.h +++ b/src/dynarmic/backend/x64/perf_map.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/cast_util.h" +#include namespace Dynarmic::Backend::X64 { @@ -17,7 +17,7 @@ void PerfMapRegister(const void* start, const void* end, std::string_view friend template void PerfMapRegister(T start, const void* end, std::string_view friendly_name) { - detail::PerfMapRegister(Common::BitCast(start), end, friendly_name); + detail::PerfMapRegister(mcl::bit_cast(start), end, friendly_name); } void PerfMapClear(); diff --git a/src/dynarmic/backend/x64/reg_alloc.cpp b/src/dynarmic/backend/x64/reg_alloc.cpp index 7ff8c780..0de490d4 100644 --- a/src/dynarmic/backend/x64/reg_alloc.cpp +++ b/src/dynarmic/backend/x64/reg_alloc.cpp @@ -10,11 +10,11 @@ #include #include +#include #include #include "dynarmic/backend/x64/abi.h" #include "dynarmic/backend/x64/stack_layout.h" -#include "dynarmic/common/assert.h" namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/backend/x64/reg_alloc.h b/src/dynarmic/backend/x64/reg_alloc.h index 5002932c..49eba4a3 100644 --- a/src/dynarmic/backend/x64/reg_alloc.h +++ b/src/dynarmic/backend/x64/reg_alloc.h @@ -11,12 +11,12 @@ #include #include +#include #include #include "dynarmic/backend/x64/block_of_code.h" #include "dynarmic/backend/x64/hostloc.h" #include "dynarmic/backend/x64/oparg.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/ir/cond.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/value.h" diff --git a/src/dynarmic/backend/x64/stack_layout.h b/src/dynarmic/backend/x64/stack_layout.h index 4b9db811..6cb1e164 100644 --- a/src/dynarmic/backend/x64/stack_layout.h +++ b/src/dynarmic/backend/x64/stack_layout.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Backend::X64 { diff --git a/src/dynarmic/common/assert.cpp b/src/dynarmic/common/assert.cpp deleted file mode 100644 index 0a905732..00000000 --- a/src/dynarmic/common/assert.cpp +++ /dev/null @@ -1,21 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2020 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#include "dynarmic/common/assert.h" - -#include -#include - -#include - -namespace Dynarmic::Common { - -[[noreturn]] void Terminate(fmt::string_view msg, fmt::format_args args) { - fmt::print(stderr, "dynarmic assertion failed: "); - fmt::vprint(stderr, msg, args); - std::terminate(); -} - -} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/assert.h b/src/dynarmic/common/assert.h deleted file mode 100644 index 5df3c4d2..00000000 --- a/src/dynarmic/common/assert.h +++ /dev/null @@ -1,71 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2020 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#include - -#include "dynarmic/common/unlikely.h" - -namespace Dynarmic::Common { - -[[noreturn]] void Terminate(fmt::string_view msg, fmt::format_args args); - -namespace detail { - -template -[[noreturn]] void TerminateHelper(fmt::string_view msg, Ts... args) { - Terminate(msg, fmt::make_format_args(args...)); -} - -} // namespace detail - -} // namespace Dynarmic::Common - -#if defined(__clang) || defined(__GNUC__) -# define ASSUME(expr) [&] { if (!(expr)) __builtin_unreachable(); }() -#elif defined(_MSC_VER) -# define ASSUME(expr) __assume(expr) -#else -# define ASSUME(expr) -#endif - -#ifdef DYNARMIC_IGNORE_ASSERTS -# if defined(__clang) || defined(__GNUC__) -# define UNREACHABLE() __builtin_unreachable() -# elif defined(_MSC_VER) -# define UNREACHABLE() __assume(0) -# else -# define UNREACHABLE() -# endif - -# define ASSERT(expr) ASSUME(expr) -# define ASSERT_MSG(expr, ...) ASSUME(expr) -# define ASSERT_FALSE(...) UNREACHABLE() -#else -# define UNREACHABLE() ASSERT_FALSE("Unreachable code!") - -# define ASSERT(expr) \ - [&] { \ - if (UNLIKELY(!(expr))) { \ - ::Dynarmic::Common::detail::TerminateHelper(#expr); \ - } \ - }() -# define ASSERT_MSG(expr, ...) \ - [&] { \ - if (UNLIKELY(!(expr))) { \ - ::Dynarmic::Common::detail::TerminateHelper(#expr "\nMessage: " __VA_ARGS__); \ - } \ - }() -# define ASSERT_FALSE(...) ::Dynarmic::Common::detail::TerminateHelper("false\nMessage: " __VA_ARGS__) -#endif - -#if defined(NDEBUG) || defined(DYNARMIC_IGNORE_ASSERTS) -# define DEBUG_ASSERT(expr) ASSUME(expr) -# define DEBUG_ASSERT_MSG(expr, ...) ASSUME(expr) -#else -# define DEBUG_ASSERT(expr) ASSERT(expr) -# define DEBUG_ASSERT_MSG(expr, ...) ASSERT_MSG(expr, __VA_ARGS__) -#endif diff --git a/src/dynarmic/common/atomic.h b/src/dynarmic/common/atomic.h index d9f00db4..8be5fc44 100644 --- a/src/dynarmic/common/atomic.h +++ b/src/dynarmic/common/atomic.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Atomic { diff --git a/src/dynarmic/common/bit_util.h b/src/dynarmic/common/bit_util.h deleted file mode 100644 index 537753a9..00000000 --- a/src/dynarmic/common/bit_util.h +++ /dev/null @@ -1,248 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2016 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#include -#include -#include -#include - -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" - -namespace Dynarmic::Common { - -/// The size of a type in terms of bits -template -constexpr size_t BitSize() { - return sizeof(T) * CHAR_BIT; -} - -template -constexpr T Ones(size_t count) { - ASSERT_MSG(count <= BitSize(), "count larger than bitsize of T"); - if (count == BitSize()) - return static_cast(~static_cast(0)); - return ~(static_cast(~static_cast(0)) << count); -} - -/// Extract bits [begin_bit, end_bit] inclusive from value of type T. -template -constexpr T Bits(const size_t begin_bit, const size_t end_bit, const T value) { - ASSERT_MSG(begin_bit <= end_bit, "invalid bit range (position of beginning bit cannot be greater than that of end bit)"); - ASSERT_MSG(begin_bit < BitSize(), "begin_bit must be smaller than size of T"); - ASSERT_MSG(end_bit < BitSize(), "end_bit must be smaller than size of T"); - - return (value >> begin_bit) & Ones(end_bit - begin_bit + 1); -} - -/// Extract bits [begin_bit, end_bit] inclusive from value of type T. -template -constexpr T Bits(const T value) { - static_assert(begin_bit <= end_bit, "invalid bit range (position of beginning bit cannot be greater than that of end bit)"); - static_assert(begin_bit < BitSize(), "begin_bit must be smaller than size of T"); - static_assert(end_bit < BitSize(), "end_bit must be smaller than size of T"); - - return (value >> begin_bit) & Ones(end_bit - begin_bit + 1); -} - -/// Create a mask of type T for bits [begin_bit, end_bit] inclusive. -template -constexpr T Mask() { - static_assert(begin_bit <= end_bit, "invalid bit range (position of beginning bit cannot be greater than that of end bit)"); - static_assert(begin_bit < BitSize(), "begin_bit must be smaller than size of T"); - static_assert(end_bit < BitSize(), "end_bit must be smaller than size of T"); - - return Ones(end_bit - begin_bit + 1) << begin_bit; -} - -/// Clears bits [begin_bit, end_bit] inclusive of value of type T. -template -constexpr T ClearBits(const T value) { - return value & ~Mask(); -} - -/// Modifies bits [begin_bit, end_bit] inclusive of value of type T. -template -constexpr T ModifyBits(const T value, const T new_bits) { - return ClearBits(value) | ((new_bits << begin_bit) & Mask()); -} - -#ifdef _MSC_VER -# pragma warning(push) -# pragma warning(disable : 4554) -#endif -/// Extracts a single bit at bit_position from value of type T. -template -inline bool Bit(size_t bit_position, const T value) { - ASSERT_MSG(bit_position < BitSize(), "bit_position must be smaller than size of T"); - - return ((value >> bit_position) & 1) != 0; -} - -/// Extracts a single bit at bit_position from value of type T. -template -constexpr bool Bit(const T value) { - static_assert(bit_position < BitSize(), "bit_position must be smaller than size of T"); - - return Bit(bit_position, value); -} - -/// Clears a single bit at bit_position from value of type T. -template -inline T ClearBit(size_t bit_position, const T value) { - ASSERT_MSG(bit_position < BitSize(), "bit_position must be smaller than size of T"); - - return value & ~(static_cast(1) << bit_position); -} - -/// Clears a single bit at bit_position from value of type T. -template -constexpr T ClearBit(const T value) { - static_assert(bit_position < BitSize(), "bit_position must be smaller than size of T"); - - return ClearBit(bit_position, value); -} - -/// Modifies a single bit at bit_position from value of type T. -template -inline T ModifyBit(size_t bit_position, const T value, bool new_bit) { - ASSERT_MSG(bit_position < BitSize(), "bit_position must be smaller than size of T"); - - return ClearBit(bit_position, value) | (static_cast(new_bit) << bit_position); -} - -/// Modifies a single bit at bit_position from value of type T. -template -constexpr T ModifyBit(const T value, bool new_bit) { - static_assert(bit_position < BitSize(), "bit_position must be smaller than size of T"); - - return ModifyBit(bit_position, value, new_bit); -} -#ifdef _MSC_VER -# pragma warning(pop) -#endif - -/// Sign-extends a value that has bit_count bits to the full bitwidth of type T. -template -constexpr T SignExtend(const T value) { - static_assert(bit_count <= BitSize(), "bit_count larger than bitsize of T"); - - constexpr T mask = static_cast(1ULL << bit_count) - 1; - const bool signbit = Bit(value); - if (signbit) { - return value | ~mask; - } - return value; -} - -/// Sign-extends a value that has bit_count bits to the full bitwidth of type T. -template -inline T SignExtend(const size_t bit_count, const T value) { - ASSERT_MSG(bit_count <= BitSize(), "bit_count larger than bitsize of T"); - - const T mask = static_cast(1ULL << bit_count) - 1; - const bool signbit = Bit(bit_count - 1, value); - if (signbit) { - return value | ~mask; - } - return value; -} - -template -inline size_t BitCount(Integral value) { - return std::bitset()>(value).count(); -} - -template -constexpr size_t CountLeadingZeros(T value) { - auto x = static_cast>(value); - size_t result = BitSize(); - while (x != 0) { - x >>= 1; - result--; - } - return result; -} - -template -constexpr int HighestSetBit(T value) { - auto x = static_cast>(value); - int result = -1; - while (x != 0) { - x >>= 1; - result++; - } - return result; -} - -template -constexpr size_t LowestSetBit(T value) { - auto x = static_cast>(value); - if (x == 0) - return BitSize(); - - size_t result = 0; - while ((x & 1) == 0) { - x >>= 1; - result++; - } - return result; -} - -template -constexpr bool MostSignificantBit(T value) { - return Bit() - 1, T>(value); -} - -template -constexpr T Replicate(T value, size_t element_size) { - ASSERT_MSG(BitSize() % element_size == 0, "bitsize of T not divisible by element_size"); - if (element_size == BitSize()) - return value; - return Replicate(T(value | value << element_size), element_size * 2); -} - -template -constexpr T RotateRight(T value, size_t amount) { - amount %= BitSize(); - - if (amount == 0) { - return value; - } - - auto x = static_cast>(value); - return static_cast((x >> amount) | (x << (BitSize() - amount))); -} - -constexpr u32 SwapHalves32(u32 value) { - return ((value & 0xFFFF0000U) >> 16) - | ((value & 0x0000FFFFU) << 16); -} - -constexpr u16 SwapBytes16(u16 value) { - return static_cast(u32{value} >> 8 | u32{value} << 8); -} - -constexpr u32 SwapBytes32(u32 value) { - return ((value & 0xFF000000U) >> 24) - | ((value & 0x00FF0000U) >> 8) - | ((value & 0x0000FF00U) << 8) - | ((value & 0x000000FFU) << 24); -} - -constexpr u64 SwapBytes64(u64 value) { - return ((value & 0xFF00000000000000ULL) >> 56) - | ((value & 0x00FF000000000000ULL) >> 40) - | ((value & 0x0000FF0000000000ULL) >> 24) - | ((value & 0x000000FF00000000ULL) >> 8) - | ((value & 0x00000000FF000000ULL) << 8) - | ((value & 0x0000000000FF0000ULL) << 24) - | ((value & 0x000000000000FF00ULL) << 40) - | ((value & 0x00000000000000FFULL) << 56); -} - -} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/cast_util.h b/src/dynarmic/common/cast_util.h index 2ac6bfc7..92c9a259 100644 --- a/src/dynarmic/common/cast_util.h +++ b/src/dynarmic/common/cast_util.h @@ -5,37 +5,10 @@ #pragma once -#include -#include - #include namespace Dynarmic::Common { -/// Reinterpret objects of one type as another by bit-casting between object representations. -template -inline Dest BitCast(const Source& source) noexcept { - static_assert(sizeof(Dest) == sizeof(Source), "size of destination and source objects must be equal"); - static_assert(std::is_trivially_copyable_v, "destination type must be trivially copyable."); - static_assert(std::is_trivially_copyable_v, "source type must be trivially copyable"); - - std::aligned_storage_t dest; - std::memcpy(&dest, &source, sizeof(dest)); - return reinterpret_cast(dest); -} - -/// Reinterpret objects of any arbitrary type as another type by bit-casting between object representations. -/// Note that here we do not verify if source has enough bytes to read from. -template -inline Dest BitCastPointee(const SourcePtr source) noexcept { - static_assert(sizeof(SourcePtr) == sizeof(void*), "source pointer must have size of a pointer"); - static_assert(std::is_trivially_copyable_v, "destination type must be trivially copyable."); - - std::aligned_storage_t dest; - std::memcpy(&dest, BitCast(source), sizeof(dest)); - return reinterpret_cast(dest); -} - /// Cast a lambda into an equivalent function pointer. template inline auto FptrCast(Function f) noexcept { diff --git a/src/dynarmic/common/common_types.h b/src/dynarmic/common/common_types.h deleted file mode 100644 index 4c36faa2..00000000 --- a/src/dynarmic/common/common_types.h +++ /dev/null @@ -1,28 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2016 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#include -#include - -using u8 = std::uint8_t; -using u16 = std::uint16_t; -using u32 = std::uint32_t; -using u64 = std::uint64_t; -using uptr = std::uintptr_t; - -using s8 = std::int8_t; -using s16 = std::int16_t; -using s32 = std::int32_t; -using s64 = std::int64_t; -using sptr = std::intptr_t; - -using size_t = std::size_t; - -using f32 = float; -using f64 = double; -static_assert(sizeof(f32) == sizeof(u32), "f32 must be 32 bits wide"); -static_assert(sizeof(f64) == sizeof(u64), "f64 must be 64 bits wide"); diff --git a/src/dynarmic/common/crypto/aes.cpp b/src/dynarmic/common/crypto/aes.cpp index 3f67dbac..c431758e 100644 --- a/src/dynarmic/common/crypto/aes.cpp +++ b/src/dynarmic/common/crypto/aes.cpp @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::AES { diff --git a/src/dynarmic/common/crypto/aes.h b/src/dynarmic/common/crypto/aes.h index 8e1e76fe..fa6d5a81 100644 --- a/src/dynarmic/common/crypto/aes.h +++ b/src/dynarmic/common/crypto/aes.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::AES { diff --git a/src/dynarmic/common/crypto/crc32.cpp b/src/dynarmic/common/crypto/crc32.cpp index 6b33a88c..c0038507 100644 --- a/src/dynarmic/common/crypto/crc32.cpp +++ b/src/dynarmic/common/crypto/crc32.cpp @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::CRC32 { diff --git a/src/dynarmic/common/crypto/crc32.h b/src/dynarmic/common/crypto/crc32.h index 11f9233e..30942327 100644 --- a/src/dynarmic/common/crypto/crc32.h +++ b/src/dynarmic/common/crypto/crc32.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::CRC32 { diff --git a/src/dynarmic/common/crypto/sm4.cpp b/src/dynarmic/common/crypto/sm4.cpp index c101634a..5743e5be 100644 --- a/src/dynarmic/common/crypto/sm4.cpp +++ b/src/dynarmic/common/crypto/sm4.cpp @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::SM4 { diff --git a/src/dynarmic/common/crypto/sm4.h b/src/dynarmic/common/crypto/sm4.h index 2444ed28..417e9b92 100644 --- a/src/dynarmic/common/crypto/sm4.h +++ b/src/dynarmic/common/crypto/sm4.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common::Crypto::SM4 { diff --git a/src/dynarmic/common/fp/fpcr.h b/src/dynarmic/common/fp/fpcr.h index 8a1b0d73..287f6d28 100644 --- a/src/dynarmic/common/fp/fpcr.h +++ b/src/dynarmic/common/fp/fpcr.h @@ -7,9 +7,10 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include + #include "dynarmic/common/fp/rounding_mode.h" namespace Dynarmic::FP { @@ -34,49 +35,49 @@ public: /// Get alternate half-precision control flag. bool AHP() const { - return Common::Bit<26>(value); + return mcl::bit::get_bit<26>(value); } /// Set alternate half-precision control flag. void AHP(bool ahp) { - value = Common::ModifyBit<26>(value, ahp); + value = mcl::bit::set_bit<26>(value, ahp); } /// Get default NaN mode control bit. bool DN() const { - return Common::Bit<25>(value); + return mcl::bit::get_bit<25>(value); } /// Set default NaN mode control bit. void DN(bool dn) { - value = Common::ModifyBit<25>(value, dn); + value = mcl::bit::set_bit<25>(value, dn); } /// Get flush-to-zero mode control bit. bool FZ() const { - return Common::Bit<24>(value); + return mcl::bit::get_bit<24>(value); } /// Set flush-to-zero mode control bit. void FZ(bool fz) { - value = Common::ModifyBit<24>(value, fz); + value = mcl::bit::set_bit<24>(value, fz); } /// Get rounding mode control field. FP::RoundingMode RMode() const { - return static_cast(Common::Bits<22, 23>(value)); + return static_cast(mcl::bit::get_bits<22, 23>(value)); } /// Set rounding mode control field. void RMode(FP::RoundingMode rounding_mode) { ASSERT_MSG(static_cast(rounding_mode) <= 0b11, "FPCR: Invalid rounding mode"); - value = Common::ModifyBits<22, 23>(value, static_cast(rounding_mode)); + value = mcl::bit::set_bits<22, 23>(value, static_cast(rounding_mode)); } /// Get the stride of a vector when executing AArch32 VFP instructions. /// This field has no function in AArch64 state. std::optional Stride() const { - switch (Common::Bits<20, 21>(value)) { + switch (mcl::bit::get_bits<20, 21>(value)) { case 0b00: return 1; case 0b11: @@ -90,90 +91,90 @@ public: /// This field has no function in AArch64 state. void Stride(size_t stride) { ASSERT_MSG(stride >= 1 && stride <= 2, "FPCR: Invalid stride"); - value = Common::ModifyBits<20, 21>(value, stride == 1 ? 0b00u : 0b11u); + value = mcl::bit::set_bits<20, 21>(value, stride == 1 ? 0b00u : 0b11u); } /// Get flush-to-zero (half-precision specific) mode control bit. bool FZ16() const { - return Common::Bit<19>(value); + return mcl::bit::get_bit<19>(value); } /// Set flush-to-zero (half-precision specific) mode control bit. void FZ16(bool fz16) { - value = Common::ModifyBit<19>(value, fz16); + value = mcl::bit::set_bit<19>(value, fz16); } /// Gets the length of a vector when executing AArch32 VFP instructions. /// This field has no function in AArch64 state. size_t Len() const { - return Common::Bits<16, 18>(value) + 1; + return mcl::bit::get_bits<16, 18>(value) + 1; } /// Sets the length of a vector when executing AArch32 VFP instructions. /// This field has no function in AArch64 state. void Len(size_t len) { ASSERT_MSG(len >= 1 && len <= 8, "FPCR: Invalid len"); - value = Common::ModifyBits<16, 18>(value, static_cast(len - 1)); + value = mcl::bit::set_bits<16, 18>(value, static_cast(len - 1)); } /// Get input denormal exception trap enable flag. bool IDE() const { - return Common::Bit<15>(value); + return mcl::bit::get_bit<15>(value); } /// Set input denormal exception trap enable flag. void IDE(bool ide) { - value = Common::ModifyBit<15>(value, ide); + value = mcl::bit::set_bit<15>(value, ide); } /// Get inexact exception trap enable flag. bool IXE() const { - return Common::Bit<12>(value); + return mcl::bit::get_bit<12>(value); } /// Set inexact exception trap enable flag. void IXE(bool ixe) { - value = Common::ModifyBit<12>(value, ixe); + value = mcl::bit::set_bit<12>(value, ixe); } /// Get underflow exception trap enable flag. bool UFE() const { - return Common::Bit<11>(value); + return mcl::bit::get_bit<11>(value); } /// Set underflow exception trap enable flag. void UFE(bool ufe) { - value = Common::ModifyBit<11>(value, ufe); + value = mcl::bit::set_bit<11>(value, ufe); } /// Get overflow exception trap enable flag. bool OFE() const { - return Common::Bit<10>(value); + return mcl::bit::get_bit<10>(value); } /// Set overflow exception trap enable flag. void OFE(bool ofe) { - value = Common::ModifyBit<10>(value, ofe); + value = mcl::bit::set_bit<10>(value, ofe); } /// Get division by zero exception trap enable flag. bool DZE() const { - return Common::Bit<9>(value); + return mcl::bit::get_bit<9>(value); } /// Set division by zero exception trap enable flag. void DZE(bool dze) { - value = Common::ModifyBit<9>(value, dze); + value = mcl::bit::set_bit<9>(value, dze); } /// Get invalid operation exception trap enable flag. bool IOE() const { - return Common::Bit<8>(value); + return mcl::bit::get_bit<8>(value); } /// Set invalid operation exception trap enable flag. void IOE(bool ioe) { - value = Common::ModifyBit<8>(value, ioe); + value = mcl::bit::set_bit<8>(value, ioe); } /// Gets the underlying raw value within the FPCR. diff --git a/src/dynarmic/common/fp/fpsr.h b/src/dynarmic/common/fp/fpsr.h index 1accf872..fba58ebb 100644 --- a/src/dynarmic/common/fp/fpsr.h +++ b/src/dynarmic/common/fp/fpsr.h @@ -5,8 +5,8 @@ #pragma once -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include namespace Dynarmic::FP { @@ -30,112 +30,112 @@ public: /// Get negative condition flag bool N() const { - return Common::Bit<31>(value); + return mcl::bit::get_bit<31>(value); } /// Set negative condition flag void N(bool N_) { - value = Common::ModifyBit<31>(value, N_); + value = mcl::bit::set_bit<31>(value, N_); } /// Get zero condition flag bool Z() const { - return Common::Bit<30>(value); + return mcl::bit::get_bit<30>(value); } /// Set zero condition flag void Z(bool Z_) { - value = Common::ModifyBit<30>(value, Z_); + value = mcl::bit::set_bit<30>(value, Z_); } /// Get carry condition flag bool C() const { - return Common::Bit<29>(value); + return mcl::bit::get_bit<29>(value); } /// Set carry condition flag void C(bool C_) { - value = Common::ModifyBit<29>(value, C_); + value = mcl::bit::set_bit<29>(value, C_); } /// Get overflow condition flag bool V() const { - return Common::Bit<28>(value); + return mcl::bit::get_bit<28>(value); } /// Set overflow condition flag void V(bool V_) { - value = Common::ModifyBit<28>(value, V_); + value = mcl::bit::set_bit<28>(value, V_); } /// Get cumulative saturation bit bool QC() const { - return Common::Bit<27>(value); + return mcl::bit::get_bit<27>(value); } /// Set cumulative saturation bit void QC(bool QC_) { - value = Common::ModifyBit<27>(value, QC_); + value = mcl::bit::set_bit<27>(value, QC_); } /// Get input denormal floating-point exception bit bool IDC() const { - return Common::Bit<7>(value); + return mcl::bit::get_bit<7>(value); } /// Set input denormal floating-point exception bit void IDC(bool IDC_) { - value = Common::ModifyBit<7>(value, IDC_); + value = mcl::bit::set_bit<7>(value, IDC_); } /// Get inexact cumulative floating-point exception bit bool IXC() const { - return Common::Bit<4>(value); + return mcl::bit::get_bit<4>(value); } /// Set inexact cumulative floating-point exception bit void IXC(bool IXC_) { - value = Common::ModifyBit<4>(value, IXC_); + value = mcl::bit::set_bit<4>(value, IXC_); } /// Get underflow cumulative floating-point exception bit bool UFC() const { - return Common::Bit<3>(value); + return mcl::bit::get_bit<3>(value); } /// Set underflow cumulative floating-point exception bit void UFC(bool UFC_) { - value = Common::ModifyBit<3>(value, UFC_); + value = mcl::bit::set_bit<3>(value, UFC_); } /// Get overflow cumulative floating-point exception bit bool OFC() const { - return Common::Bit<2>(value); + return mcl::bit::get_bit<2>(value); } /// Set overflow cumulative floating-point exception bit void OFC(bool OFC_) { - value = Common::ModifyBit<2>(value, OFC_); + value = mcl::bit::set_bit<2>(value, OFC_); } /// Get divide by zero cumulative floating-point exception bit bool DZC() const { - return Common::Bit<1>(value); + return mcl::bit::get_bit<1>(value); } /// Set divide by zero cumulative floating-point exception bit void DZC(bool DZC_) { - value = Common::ModifyBit<1>(value, DZC_); + value = mcl::bit::set_bit<1>(value, DZC_); } /// Get invalid operation cumulative floating-point exception bit bool IOC() const { - return Common::Bit<0>(value); + return mcl::bit::get_bit<0>(value); } /// Set invalid operation cumulative floating-point exception bit void IOC(bool IOC_) { - value = Common::ModifyBit<0>(value, IOC_); + value = mcl::bit::set_bit<0>(value, IOC_); } /// Gets the underlying raw value within the FPSR. diff --git a/src/dynarmic/common/fp/fused.cpp b/src/dynarmic/common/fp/fused.cpp index 2f3ccacb..883de651 100644 --- a/src/dynarmic/common/fp/fused.cpp +++ b/src/dynarmic/common/fp/fused.cpp @@ -5,6 +5,8 @@ #include "dynarmic/common/fp/fused.h" +#include + #include "dynarmic/common/fp/mantissa_util.h" #include "dynarmic/common/fp/unpacked.h" #include "dynarmic/common/u128.h" @@ -81,7 +83,7 @@ FPUnpacked FusedMulAdd(FPUnpacked addend, FPUnpacked op1, FPUnpacked op2) { return FPUnpacked{result_sign, result_exponent, result.lower}; } - const int required_shift = normalized_point_position - Common::HighestSetBit(result.upper); + const int required_shift = normalized_point_position - mcl::bit::highest_set_bit(result.upper); result = result << required_shift; result_exponent -= required_shift; return ReduceMantissa(result_sign, result_exponent, result); diff --git a/src/dynarmic/common/fp/info.h b/src/dynarmic/common/fp/info.h index f5a7b57f..8cc2d29d 100644 --- a/src/dynarmic/common/fp/info.h +++ b/src/dynarmic/common/fp/info.h @@ -5,8 +5,8 @@ #pragma once -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include namespace Dynarmic::FP { @@ -124,7 +124,7 @@ constexpr FPT FPValue() { } constexpr int point_position = static_cast(FPInfo::explicit_mantissa_width); - constexpr int highest_bit = Common::HighestSetBit(value); + constexpr int highest_bit = mcl::bit::highest_set_bit(value); constexpr int offset = point_position - highest_bit; constexpr int normalized_exponent = exponent - offset + point_position; static_assert(offset >= 0); diff --git a/src/dynarmic/common/fp/mantissa_util.h b/src/dynarmic/common/fp/mantissa_util.h index a2fe7c21..31be52f7 100644 --- a/src/dynarmic/common/fp/mantissa_util.h +++ b/src/dynarmic/common/fp/mantissa_util.h @@ -5,8 +5,9 @@ #pragma once -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include namespace Dynarmic::FP { @@ -22,13 +23,13 @@ inline ResidualError ResidualErrorOnRightShift(u64 mantissa, int shift_amount) { return ResidualError::Zero; } - if (shift_amount > static_cast(Common::BitSize())) { - return Common::MostSignificantBit(mantissa) ? ResidualError::GreaterThanHalf : ResidualError::LessThanHalf; + if (shift_amount > static_cast(mcl::bitsizeof)) { + return mcl::bit::most_significant_bit(mantissa) ? ResidualError::GreaterThanHalf : ResidualError::LessThanHalf; } const size_t half_bit_position = static_cast(shift_amount - 1); const u64 half = static_cast(1) << half_bit_position; - const u64 error_mask = Common::Ones(static_cast(shift_amount)); + const u64 error_mask = mcl::bit::ones(static_cast(shift_amount)); const u64 error = mantissa & error_mask; if (error == 0) { diff --git a/src/dynarmic/common/fp/op/FPConvert.cpp b/src/dynarmic/common/fp/op/FPConvert.cpp index 8d01e524..85f1eaf8 100644 --- a/src/dynarmic/common/fp/op/FPConvert.cpp +++ b/src/dynarmic/common/fp/op/FPConvert.cpp @@ -5,7 +5,10 @@ #include "dynarmic/common/fp/op/FPConvert.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" @@ -16,27 +19,27 @@ namespace Dynarmic::FP { namespace { template FPT_TO FPConvertNaN(FPT_FROM op) { - const bool sign = Common::Bit() - 1>(op); + const bool sign = mcl::bit::get_bit - 1>(op); const u64 frac = [op] { if constexpr (sizeof(FPT_FROM) == sizeof(u64)) { - return Common::Bits<0, 50>(op); + return mcl::bit::get_bits<0, 50>(op); } else if constexpr (sizeof(FPT_FROM) == sizeof(u32)) { - return u64{Common::Bits<0, 21>(op)} << 29; + return u64{mcl::bit::get_bits<0, 21>(op)} << 29; } else { - return u64{Common::Bits<0, 8>(op)} << 42; + return u64{mcl::bit::get_bits<0, 8>(op)} << 42; } }(); - const size_t dest_bit_size = Common::BitSize(); + const size_t dest_bit_size = mcl::bitsizeof; const u64 shifted_sign = u64{sign} << (dest_bit_size - 1); - const u64 exponent = Common::Ones(dest_bit_size - FPInfo::explicit_mantissa_width); + const u64 exponent = mcl::bit::ones(dest_bit_size - FPInfo::explicit_mantissa_width); if constexpr (sizeof(FPT_TO) == sizeof(u64)) { return FPT_TO(shifted_sign | exponent << 51 | frac); } else if constexpr (sizeof(FPT_TO) == sizeof(u32)) { - return FPT_TO(shifted_sign | exponent << 22 | Common::Bits<29, 50>(frac)); + return FPT_TO(shifted_sign | exponent << 22 | mcl::bit::get_bits<29, 50>(frac)); } else { - return FPT_TO(shifted_sign | exponent << 9 | Common::Bits<42, 50>(frac)); + return FPT_TO(shifted_sign | exponent << 9 | mcl::bit::get_bits<42, 50>(frac)); } } } // Anonymous namespace @@ -44,7 +47,7 @@ FPT_TO FPConvertNaN(FPT_FROM op) { template FPT_TO FPConvert(FPT_FROM op, FPCR fpcr, RoundingMode rounding_mode, FPSR& fpsr) { const auto [type, sign, value] = FPUnpackCV(op, fpcr, fpsr); - const bool is_althp = Common::BitSize() == 16 && fpcr.AHP(); + const bool is_althp = mcl::bitsizeof == 16 && fpcr.AHP(); if (type == FPType::SNaN || type == FPType::QNaN) { std::uintmax_t result{}; diff --git a/src/dynarmic/common/fp/op/FPMulAdd.cpp b/src/dynarmic/common/fp/op/FPMulAdd.cpp index 409b750b..be699ef8 100644 --- a/src/dynarmic/common/fp/op/FPMulAdd.cpp +++ b/src/dynarmic/common/fp/op/FPMulAdd.cpp @@ -5,7 +5,8 @@ #include "dynarmic/common/fp/op/FPMulAdd.h" -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/fused.h" diff --git a/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp b/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp index 4f547e9d..ed28bcc5 100644 --- a/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp +++ b/src/dynarmic/common/fp/op/FPRSqrtEstimate.cpp @@ -5,7 +5,8 @@ #include "dynarmic/common/fp/op/FPRSqrtEstimate.h" -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" diff --git a/src/dynarmic/common/fp/op/FPRecipEstimate.cpp b/src/dynarmic/common/fp/op/FPRecipEstimate.cpp index 956c7819..1fd4b924 100644 --- a/src/dynarmic/common/fp/op/FPRecipEstimate.cpp +++ b/src/dynarmic/common/fp/op/FPRecipEstimate.cpp @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" diff --git a/src/dynarmic/common/fp/op/FPRecipExponent.cpp b/src/dynarmic/common/fp/op/FPRecipExponent.cpp index 7bbcb8cc..171b94e9 100644 --- a/src/dynarmic/common/fp/op/FPRecipExponent.cpp +++ b/src/dynarmic/common/fp/op/FPRecipExponent.cpp @@ -5,8 +5,9 @@ #include "dynarmic/common/fp/op/FPRecipExponent.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" @@ -18,11 +19,11 @@ namespace { template FPT DetermineExponentValue(size_t value) { if constexpr (sizeof(FPT) == sizeof(u32)) { - return static_cast(Common::Bits<23, 30>(value)); + return static_cast(mcl::bit::get_bits<23, 30>(value)); } else if constexpr (sizeof(FPT) == sizeof(u64)) { - return static_cast(Common::Bits<52, 62>(value)); + return static_cast(mcl::bit::get_bits<52, 62>(value)); } else { - return static_cast(Common::Bits<10, 14>(value)); + return static_cast(mcl::bit::get_bits<10, 14>(value)); } } } // Anonymous namespace @@ -41,7 +42,7 @@ FPT FPRecipExponent(FPT op, FPCR fpcr, FPSR& fpsr) { // Zero and denormals if (exponent == 0) { - const FPT max_exponent = Common::Ones(FPInfo::exponent_width) - 1; + const FPT max_exponent = mcl::bit::ones(FPInfo::exponent_width) - 1; return FPT(sign_bits | (max_exponent << FPInfo::explicit_mantissa_width)); } diff --git a/src/dynarmic/common/fp/op/FPRoundInt.cpp b/src/dynarmic/common/fp/op/FPRoundInt.cpp index 6721228b..73259090 100644 --- a/src/dynarmic/common/fp/op/FPRoundInt.cpp +++ b/src/dynarmic/common/fp/op/FPRoundInt.cpp @@ -5,9 +5,10 @@ #include "dynarmic/common/fp/op/FPRoundInt.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" @@ -53,7 +54,7 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) bool round_up = false; switch (rounding) { case RoundingMode::ToNearest_TieEven: - round_up = error > ResidualError::Half || (error == ResidualError::Half && Common::Bit<0>(int_result)); + round_up = error > ResidualError::Half || (error == ResidualError::Half && mcl::bit::get_bit<0>(int_result)); break; case RoundingMode::TowardsPlusInfinity: round_up = error != ResidualError::Zero; @@ -62,10 +63,10 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) round_up = false; break; case RoundingMode::TowardsZero: - round_up = error != ResidualError::Zero && Common::MostSignificantBit(int_result); + round_up = error != ResidualError::Zero && mcl::bit::most_significant_bit(int_result); break; case RoundingMode::ToNearest_TieAwayFromZero: - round_up = error > ResidualError::Half || (error == ResidualError::Half && !Common::MostSignificantBit(int_result)); + round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result)); break; case RoundingMode::ToOdd: UNREACHABLE(); @@ -75,7 +76,7 @@ u64 FPRoundInt(FPT op, FPCR fpcr, RoundingMode rounding, bool exact, FPSR& fpsr) int_result++; } - const bool new_sign = Common::MostSignificantBit(int_result); + const bool new_sign = mcl::bit::most_significant_bit(int_result); const u64 abs_int_result = new_sign ? Safe::Negate(int_result) : static_cast(int_result); const FPT result = int_result == 0 diff --git a/src/dynarmic/common/fp/op/FPRoundInt.h b/src/dynarmic/common/fp/op/FPRoundInt.h index e8d0609a..e326627c 100644 --- a/src/dynarmic/common/fp/op/FPRoundInt.h +++ b/src/dynarmic/common/fp/op/FPRoundInt.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/src/dynarmic/common/fp/op/FPToFixed.cpp b/src/dynarmic/common/fp/op/FPToFixed.cpp index 011ec4e8..adb90180 100644 --- a/src/dynarmic/common/fp/op/FPToFixed.cpp +++ b/src/dynarmic/common/fp/op/FPToFixed.cpp @@ -5,9 +5,11 @@ #include "dynarmic/common/fp/op/FPToFixed.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/mantissa_util.h" @@ -50,7 +52,7 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou bool round_up = false; switch (rounding) { case RoundingMode::ToNearest_TieEven: - round_up = error > ResidualError::Half || (error == ResidualError::Half && Common::Bit<0>(int_result)); + round_up = error > ResidualError::Half || (error == ResidualError::Half && mcl::bit::get_bit<0>(int_result)); break; case RoundingMode::TowardsPlusInfinity: round_up = error != ResidualError::Zero; @@ -59,10 +61,10 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou round_up = false; break; case RoundingMode::TowardsZero: - round_up = error != ResidualError::Zero && Common::MostSignificantBit(int_result); + round_up = error != ResidualError::Zero && mcl::bit::most_significant_bit(int_result); break; case RoundingMode::ToNearest_TieAwayFromZero: - round_up = error > ResidualError::Half || (error == ResidualError::Half && !Common::MostSignificantBit(int_result)); + round_up = error > ResidualError::Half || (error == ResidualError::Half && !mcl::bit::most_significant_bit(int_result)); break; case RoundingMode::ToOdd: UNREACHABLE(); @@ -73,12 +75,12 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou } // Detect Overflow - const int min_exponent_for_overflow = static_cast(ibits) - static_cast(Common::HighestSetBit(value.mantissa + (round_up ? 1 : 0))) - (unsigned_ ? 0 : 1); + const int min_exponent_for_overflow = static_cast(ibits) - static_cast(mcl::bit::highest_set_bit(value.mantissa + (round_up ? 1 : 0))) - (unsigned_ ? 0 : 1); if (exponent >= min_exponent_for_overflow) { // Positive overflow if (unsigned_ || !sign) { FPProcessException(FPExc::InvalidOp, fpcr, fpsr); - return Common::Ones(ibits - (unsigned_ ? 0 : 1)); + return mcl::bit::ones(ibits - (unsigned_ ? 0 : 1)); } // Negative overflow @@ -92,7 +94,7 @@ u64 FPToFixed(size_t ibits, FPT op, size_t fbits, bool unsigned_, FPCR fpcr, Rou if (error != ResidualError::Zero) { FPProcessException(FPExc::Inexact, fpcr, fpsr); } - return int_result & Common::Ones(ibits); + return int_result & mcl::bit::ones(ibits); } template u64 FPToFixed(size_t ibits, u16 op, size_t fbits, bool unsigned_, FPCR fpcr, RoundingMode rounding, FPSR& fpsr); diff --git a/src/dynarmic/common/fp/op/FPToFixed.h b/src/dynarmic/common/fp/op/FPToFixed.h index e87565a4..53a95283 100644 --- a/src/dynarmic/common/fp/op/FPToFixed.h +++ b/src/dynarmic/common/fp/op/FPToFixed.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::FP { diff --git a/src/dynarmic/common/fp/process_exception.cpp b/src/dynarmic/common/fp/process_exception.cpp index a934118f..a97e0ec8 100644 --- a/src/dynarmic/common/fp/process_exception.cpp +++ b/src/dynarmic/common/fp/process_exception.cpp @@ -5,7 +5,8 @@ #include "dynarmic/common/fp/process_exception.h" -#include "dynarmic/common/assert.h" +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" diff --git a/src/dynarmic/common/fp/process_nan.cpp b/src/dynarmic/common/fp/process_nan.cpp index 0e2891dc..516b92ad 100644 --- a/src/dynarmic/common/fp/process_nan.cpp +++ b/src/dynarmic/common/fp/process_nan.cpp @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" @@ -26,7 +27,7 @@ FPT FPProcessNaN(FPType type, FPT op, FPCR fpcr, FPSR& fpsr) { FPT result = op; if (type == FPType::SNaN) { - result = Common::ModifyBit(op, true); + result = mcl::bit::set_bit(op, true); FPProcessException(FPExc::InvalidOp, fpcr, fpsr); } diff --git a/src/dynarmic/common/fp/unpacked.cpp b/src/dynarmic/common/fp/unpacked.cpp index 7b4c1a68..f853ab07 100644 --- a/src/dynarmic/common/fp/unpacked.cpp +++ b/src/dynarmic/common/fp/unpacked.cpp @@ -7,6 +7,9 @@ #include +#include +#include + #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/info.h" #include "dynarmic/common/fp/mantissa_util.h" @@ -26,9 +29,9 @@ std::tuple FPUnpackBase(FPT op, FPCR fpcr, [[maybe_unu constexpr int denormal_exponent = FPInfo::exponent_min - int(FPInfo::explicit_mantissa_width); constexpr bool is_half_precision = std::is_same_v; - const bool sign = Common::Bit(op); - const FPT exp_raw = Common::Bits(op); - const FPT frac_raw = Common::Bits(op); + const bool sign = mcl::bit::get_bit(op); + const FPT exp_raw = mcl::bit::get_bits(op); + const FPT frac_raw = mcl::bit::get_bits(op); if (exp_raw == 0) { if constexpr (is_half_precision) { @@ -48,14 +51,14 @@ std::tuple FPUnpackBase(FPT op, FPCR fpcr, [[maybe_unu } } - const bool exp_all_ones = exp_raw == Common::Ones(FPInfo::exponent_width); + const bool exp_all_ones = exp_raw == mcl::bit::ones(FPInfo::exponent_width); const bool ahp_disabled = is_half_precision && !fpcr.AHP(); if ((exp_all_ones && !is_half_precision) || (exp_all_ones && ahp_disabled)) { if (frac_raw == 0) { return {FPType::Infinity, sign, ToNormalized(sign, 1000000, 1)}; } - const bool is_quiet = Common::Bit(frac_raw); + const bool is_quiet = mcl::bit::get_bit(frac_raw); return {is_quiet ? FPType::QNaN : FPType::SNaN, sign, {sign, 0, 0}}; } @@ -70,7 +73,7 @@ template std::tuple FPUnpackBase(u64 op, FPCR fpc template std::tuple Normalize(FPUnpacked op, int extra_right_shift = 0) { - const int highest_set_bit = Common::HighestSetBit(op.mantissa); + const int highest_set_bit = mcl::bit::highest_set_bit(op.mantissa); const int shift_amount = highest_set_bit - static_cast(F) + extra_right_shift; const u64 mantissa = Safe::LogicalShiftRight(op.mantissa, shift_amount); const ResidualError error = ResidualErrorOnRightShift(op.mantissa, shift_amount); @@ -107,7 +110,7 @@ FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) { bool round_up = false, overflow_to_inf = false; switch (rounding) { case RoundingMode::ToNearest_TieEven: { - round_up = (error > ResidualError::Half) || (error == ResidualError::Half && Common::Bit<0>(mantissa)); + round_up = (error > ResidualError::Half) || (error == ResidualError::Half && mcl::bit::get_bit<0>(mantissa)); overflow_to_inf = true; break; } @@ -141,7 +144,7 @@ FPT FPRoundBase(FPUnpacked op, FPCR fpcr, RoundingMode rounding, FPSR& fpsr) { } if (error != ResidualError::Zero && rounding == RoundingMode::ToOdd) { - mantissa = Common::ModifyBit<0>(mantissa, true); + mantissa = mcl::bit::set_bit<0>(mantissa, true); } FPT result = 0; diff --git a/src/dynarmic/common/fp/unpacked.h b/src/dynarmic/common/fp/unpacked.h index 5b252805..77f33d89 100644 --- a/src/dynarmic/common/fp/unpacked.h +++ b/src/dynarmic/common/fp/unpacked.h @@ -7,7 +7,9 @@ #include -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/fp/fpcr.h" namespace Dynarmic::FP { @@ -43,7 +45,7 @@ constexpr FPUnpacked ToNormalized(bool sign, int exponent, u64 value) { return {sign, 0, 0}; } - const int highest_bit = Common::HighestSetBit(value); + const int highest_bit = mcl::bit::highest_set_bit(value); const int offset = static_cast(normalized_point_position) - highest_bit; value <<= offset; exponent -= offset - static_cast(normalized_point_position); diff --git a/src/dynarmic/common/intrusive_list.h b/src/dynarmic/common/intrusive_list.h deleted file mode 100644 index 7ee8e439..00000000 --- a/src/dynarmic/common/intrusive_list.h +++ /dev/null @@ -1,379 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2016 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#include -#include -#include -#include - -#include "dynarmic/common/assert.h" - -namespace Dynarmic::Common { - -template -class IntrusiveList; -template -class IntrusiveListIterator; - -template -class IntrusiveListNode { -public: - bool IsSentinel() const { - return is_sentinel; - } - -protected: - IntrusiveListNode* next = nullptr; - IntrusiveListNode* prev = nullptr; - bool is_sentinel = false; - - friend class IntrusiveList; - friend class IntrusiveListIterator; - friend class IntrusiveListIterator; -}; - -template -class IntrusiveListSentinel final : public IntrusiveListNode { - using IntrusiveListNode::next; - using IntrusiveListNode::prev; - using IntrusiveListNode::is_sentinel; - -public: - IntrusiveListSentinel() { - next = this; - prev = this; - is_sentinel = true; - } -}; - -template -class IntrusiveListIterator { -public: - using iterator_category = std::bidirectional_iterator_tag; - using difference_type = std::ptrdiff_t; - using value_type = T; - using pointer = value_type*; - using const_pointer = const value_type*; - using reference = value_type&; - using const_reference = const value_type&; - - // If value_type is const, we want "const IntrusiveListNode", not "const IntrusiveListNode" - using node_type = std::conditional_t::value, - const IntrusiveListNode>, - IntrusiveListNode>; - using node_pointer = node_type*; - using node_reference = node_type&; - - IntrusiveListIterator() = default; - IntrusiveListIterator(const IntrusiveListIterator& other) = default; - IntrusiveListIterator& operator=(const IntrusiveListIterator& other) = default; - - explicit IntrusiveListIterator(node_pointer list_node) - : node(list_node) { - } - explicit IntrusiveListIterator(pointer data) - : node(data) { - } - explicit IntrusiveListIterator(reference data) - : node(&data) { - } - - IntrusiveListIterator& operator++() { - node = node->next; - return *this; - } - IntrusiveListIterator& operator--() { - node = node->prev; - return *this; - } - IntrusiveListIterator operator++(int) { - IntrusiveListIterator it(*this); - ++*this; - return it; - } - IntrusiveListIterator operator--(int) { - IntrusiveListIterator it(*this); - --*this; - return it; - } - - bool operator==(const IntrusiveListIterator& other) const { - return node == other.node; - } - bool operator!=(const IntrusiveListIterator& other) const { - return !operator==(other); - } - - reference operator*() const { - DEBUG_ASSERT(!node->IsSentinel()); - return static_cast(*node); - } - pointer operator->() const { - return std::addressof(operator*()); - } - - node_pointer AsNodePointer() const { - return node; - } - -private: - friend class IntrusiveList; - node_pointer node = nullptr; -}; - -template -class IntrusiveList { -public: - using difference_type = std::ptrdiff_t; - using size_type = std::size_t; - using value_type = T; - using pointer = value_type*; - using const_pointer = const value_type*; - using reference = value_type&; - using const_reference = const value_type&; - using iterator = IntrusiveListIterator; - using const_iterator = IntrusiveListIterator; - using reverse_iterator = std::reverse_iterator; - using const_reverse_iterator = std::reverse_iterator; - - /** - * Inserts a node at the given location indicated by an iterator. - * - * @param location The location to insert the node. - * @param new_node The node to add. - */ - iterator insert(iterator location, pointer new_node) { - return insert_before(location, new_node); - } - - /** - * Inserts a node at the given location, moving the previous - * node occupant ahead of the one inserted. - * - * @param location The location to insert the new node. - * @param new_node The node to insert into the list. - */ - iterator insert_before(iterator location, pointer new_node) { - auto existing_node = location.AsNodePointer(); - - new_node->next = existing_node; - new_node->prev = existing_node->prev; - existing_node->prev->next = new_node; - existing_node->prev = new_node; - - return iterator(new_node); - } - - /** - * Inserts a new node into the list ahead of the position indicated. - * - * @param position Location to insert the node in front of. - * @param new_node The node to be inserted into the list. - */ - iterator insert_after(iterator position, pointer new_node) { - if (empty()) - return insert(begin(), new_node); - - return insert(++position, new_node); - } - - /** - * Add an entry to the start of the list. - * @param node Node to add to the list. - */ - void push_front(pointer node) { - insert(begin(), node); - } - - /** - * Add an entry to the end of the list - * @param node Node to add to the list. - */ - void push_back(pointer node) { - insert(end(), node); - } - - /** - * Erases the node at the front of the list. - * @note Must not be called on an empty list. - */ - void pop_front() { - DEBUG_ASSERT(!empty()); - erase(begin()); - } - - /** - * Erases the node at the back of the list. - * @note Must not be called on an empty list. - */ - void pop_back() { - DEBUG_ASSERT(!empty()); - erase(--end()); - } - - /** - * Removes a node from this list - * @param it An iterator that points to the node to remove from list. - */ - pointer remove(iterator& it) { - DEBUG_ASSERT(it != end()); - - pointer node = &*it++; - - node->prev->next = node->next; - node->next->prev = node->prev; -#if !defined(NDEBUG) - node->next = nullptr; - node->prev = nullptr; -#endif - - return node; - } - - /** - * Removes a node from this list - * @param it A constant iterator that points to the node to remove from list. - */ - pointer remove(const iterator& it) { - iterator copy = it; - return remove(copy); - } - - /** - * Removes a node from this list. - * @param node A pointer to the node to remove. - */ - pointer remove(pointer node) { - return remove(iterator(node)); - } - - /** - * Removes a node from this list. - * @param node A reference to the node to remove. - */ - pointer remove(reference node) { - return remove(iterator(node)); - } - - /** - * Is this list empty? - * @returns true if there are no nodes in this list. - */ - bool empty() const { - return root->next == root.get(); - } - - /** - * Gets the total number of elements within this list. - * @return the number of elements in this list. - */ - size_type size() const { - return static_cast(std::distance(begin(), end())); - } - - /** - * Retrieves a reference to the node at the front of the list. - * @note Must not be called on an empty list. - */ - reference front() { - DEBUG_ASSERT(!empty()); - return *begin(); - } - - /** - * Retrieves a constant reference to the node at the front of the list. - * @note Must not be called on an empty list. - */ - const_reference front() const { - DEBUG_ASSERT(!empty()); - return *begin(); - } - - /** - * Retrieves a reference to the node at the back of the list. - * @note Must not be called on an empty list. - */ - reference back() { - DEBUG_ASSERT(!empty()); - return *--end(); - } - - /** - * Retrieves a constant reference to the node at the back of the list. - * @note Must not be called on an empty list. - */ - const_reference back() const { - DEBUG_ASSERT(!empty()); - return *--end(); - } - - // Iterator interface - iterator begin() { return iterator(root->next); } - const_iterator begin() const { return const_iterator(root->next); } - const_iterator cbegin() const { return begin(); } - - iterator end() { return iterator(root.get()); } - const_iterator end() const { return const_iterator(root.get()); } - const_iterator cend() const { return end(); } - - reverse_iterator rbegin() { return reverse_iterator(end()); } - const_reverse_iterator rbegin() const { return const_reverse_iterator(end()); } - const_reverse_iterator crbegin() const { return rbegin(); } - - reverse_iterator rend() { return reverse_iterator(begin()); } - const_reverse_iterator rend() const { return const_reverse_iterator(begin()); } - const_reverse_iterator crend() const { return rend(); } - - /** - * Erases a node from the list, indicated by an iterator. - * @param it The iterator that points to the node to erase. - */ - iterator erase(iterator it) { - remove(it); - return it; - } - - /** - * Erases a node from this list. - * @param node A pointer to the node to erase from this list. - */ - iterator erase(pointer node) { - return erase(iterator(node)); - } - - /** - * Erases a node from this list. - * @param node A reference to the node to erase from this list. - */ - iterator erase(reference node) { - return erase(iterator(node)); - } - - /** - * Exchanges contents of this list with another list instance. - * @param other The other list to swap with. - */ - void swap(IntrusiveList& other) noexcept { - root.swap(other.root); - } - -private: - std::shared_ptr> root = std::make_shared>(); -}; - -/** - * Exchanges contents of an intrusive list with another intrusive list. - * @tparam T The type of data being kept track of by the lists. - * @param lhs The first list. - * @param rhs The second list. - */ -template -void swap(IntrusiveList& lhs, IntrusiveList& rhs) noexcept { - lhs.swap(rhs); -} - -} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/iterator_util.h b/src/dynarmic/common/iterator_util.h deleted file mode 100644 index 982f5313..00000000 --- a/src/dynarmic/common/iterator_util.h +++ /dev/null @@ -1,35 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2016 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#include - -namespace Dynarmic::Common { -namespace detail { - -template -struct ReverseAdapter { - T& iterable; - - constexpr auto begin() { - using namespace std; - return rbegin(iterable); - } - - constexpr auto end() { - using namespace std; - return rend(iterable); - } -}; - -} // namespace detail - -template -constexpr detail::ReverseAdapter Reverse(T&& iterable) { - return detail::ReverseAdapter{iterable}; -} - -} // namespace Dynarmic::Common diff --git a/src/dynarmic/common/llvm_disassemble.cpp b/src/dynarmic/common/llvm_disassemble.cpp index 614dff4f..72dfafd4 100644 --- a/src/dynarmic/common/llvm_disassemble.cpp +++ b/src/dynarmic/common/llvm_disassemble.cpp @@ -12,9 +12,10 @@ # include #endif -#include "dynarmic/common/assert.h" -#include "dynarmic/common/cast_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include + #include "dynarmic/common/llvm_disassemble.h" namespace Dynarmic::Common { @@ -49,7 +50,7 @@ std::string DisassembleX64(const void* begin, const void* end) { LLVMDisasmDispose(llvm_ctx); #else result += fmt::format("(recompile with DYNARMIC_USE_LLVM=ON to disassemble the generated x86_64 code)\n"); - result += fmt::format("start: {:016x}, end: {:016x}\n", BitCast(begin), BitCast(end)); + result += fmt::format("start: {:016x}, end: {:016x}\n", mcl::bit_cast(begin), mcl::bit_cast(end)); #endif return result; diff --git a/src/dynarmic/common/llvm_disassemble.h b/src/dynarmic/common/llvm_disassemble.h index 16dc15f8..56de791a 100644 --- a/src/dynarmic/common/llvm_disassemble.h +++ b/src/dynarmic/common/llvm_disassemble.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/src/dynarmic/common/macro_util.h b/src/dynarmic/common/macro_util.h deleted file mode 100644 index 2ccb33bd..00000000 --- a/src/dynarmic/common/macro_util.h +++ /dev/null @@ -1,15 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2018 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#define CONCATENATE_TOKENS(x, y) CONCATENATE_TOKENS_IMPL(x, y) -#define CONCATENATE_TOKENS_IMPL(x, y) x##y - -#ifdef __COUNTER__ -# define ANONYMOUS_VARIABLE(str) CONCATENATE_TOKENS(str, __COUNTER__) -#else -# define ANONYMOUS_VARIABLE(str) CONCATENATE_TOKENS(str, __LINE__) -#endif diff --git a/src/dynarmic/common/math_util.h b/src/dynarmic/common/math_util.h index 9006fb2d..5c1f784c 100644 --- a/src/dynarmic/common/math_util.h +++ b/src/dynarmic/common/math_util.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/src/dynarmic/common/safe_ops.h b/src/dynarmic/common/safe_ops.h index 50e20fbf..aef31347 100644 --- a/src/dynarmic/common/safe_ops.h +++ b/src/dynarmic/common/safe_ops.h @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/u128.h" namespace Dynarmic::Safe { @@ -26,7 +27,7 @@ template T LogicalShiftLeft(T value, int shift_amount) { static_assert(std::is_integral_v); - if (shift_amount >= static_cast(Common::BitSize())) { + if (shift_amount >= static_cast(mcl::bitsizeof)) { return 0; } @@ -47,7 +48,7 @@ template T LogicalShiftRight(T value, int shift_amount) { static_assert(std::is_integral_v); - if (shift_amount >= static_cast(Common::BitSize())) { + if (shift_amount >= static_cast(mcl::bitsizeof)) { return 0; } @@ -66,14 +67,14 @@ inline u128 LogicalShiftRight(u128 value, int shift_amount) { template T LogicalShiftRightDouble(T top, T bottom, int shift_amount) { - return LogicalShiftLeft(top, int(Common::BitSize()) - shift_amount) | LogicalShiftRight(bottom, shift_amount); + return LogicalShiftLeft(top, int(mcl::bitsizeof) - shift_amount) | LogicalShiftRight(bottom, shift_amount); } template T ArithmeticShiftLeft(T value, int shift_amount) { static_assert(std::is_integral_v); - if (shift_amount >= static_cast(Common::BitSize())) { + if (shift_amount >= static_cast(mcl::bitsizeof)) { return 0; } @@ -89,8 +90,8 @@ template T ArithmeticShiftRight(T value, int shift_amount) { static_assert(std::is_integral_v); - if (shift_amount >= static_cast(Common::BitSize())) { - return Common::MostSignificantBit(value) ? ~static_cast(0) : 0; + if (shift_amount >= static_cast(mcl::bitsizeof)) { + return mcl::bit::most_significant_bit(value) ? ~static_cast(0) : 0; } if (shift_amount < 0) { @@ -103,7 +104,7 @@ T ArithmeticShiftRight(T value, int shift_amount) { template T ArithmeticShiftRightDouble(T top, T bottom, int shift_amount) { - return ArithmeticShiftLeft(top, int(Common::BitSize()) - shift_amount) | LogicalShiftRight(bottom, shift_amount); + return ArithmeticShiftLeft(top, int(mcl::bitsizeof) - shift_amount) | LogicalShiftRight(bottom, shift_amount); } template diff --git a/src/dynarmic/common/scope_exit.h b/src/dynarmic/common/scope_exit.h deleted file mode 100644 index 4801f135..00000000 --- a/src/dynarmic/common/scope_exit.h +++ /dev/null @@ -1,86 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2018 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#include -#include -#include - -#include "dynarmic/common/macro_util.h" - -namespace Dynarmic::detail { - -struct ScopeExitTag {}; -struct ScopeFailTag {}; -struct ScopeSuccessTag {}; - -template -class ScopeExit final { -public: - explicit ScopeExit(Function&& fn) - : function(std::move(fn)) {} - ~ScopeExit() noexcept { - function(); - } - -private: - Function function; -}; - -template -class ScopeFail final { -public: - explicit ScopeFail(Function&& fn) - : function(std::move(fn)), exception_count(std::uncaught_exceptions()) {} - ~ScopeFail() noexcept { - if (std::uncaught_exceptions() > exception_count) { - function(); - } - } - -private: - Function function; - int exception_count; -}; - -template -class ScopeSuccess final { -public: - explicit ScopeSuccess(Function&& fn) - : function(std::move(fn)), exception_count(std::uncaught_exceptions()) {} - ~ScopeSuccess() { - if (std::uncaught_exceptions() <= exception_count) { - function(); - } - } - -private: - Function function; - int exception_count; -}; - -// We use ->* here as it has the highest precedence of the operators we can use. - -template -auto operator->*(ScopeExitTag, Function&& function) { - return ScopeExit>{std::forward(function)}; -} - -template -auto operator->*(ScopeFailTag, Function&& function) { - return ScopeFail>{std::forward(function)}; -} - -template -auto operator->*(ScopeSuccessTag, Function&& function) { - return ScopeSuccess>{std::forward(function)}; -} - -} // namespace Dynarmic::detail - -#define SCOPE_EXIT auto ANONYMOUS_VARIABLE(_SCOPE_EXIT_) = ::Dynarmic::detail::ScopeExitTag{}->*[&]() noexcept -#define SCOPE_FAIL auto ANONYMOUS_VARIABLE(_SCOPE_FAIL_) = ::Dynarmic::detail::ScopeFailTag{}->*[&]() noexcept -#define SCOPE_SUCCESS auto ANONYMOUS_VARIABLE(_SCOPE_FAIL_) = ::Dynarmic::detail::ScopeSuccessTag{}->*[&]() diff --git a/src/dynarmic/common/u128.cpp b/src/dynarmic/common/u128.cpp index 81aa0cf9..a19269e8 100644 --- a/src/dynarmic/common/u128.cpp +++ b/src/dynarmic/common/u128.cpp @@ -5,7 +5,8 @@ #include "dynarmic/common/u128.h" -#include "dynarmic/common/common_types.h" +#include +#include namespace Dynarmic { diff --git a/src/dynarmic/common/u128.h b/src/dynarmic/common/u128.h index 415173b0..f6df1ae6 100644 --- a/src/dynarmic/common/u128.h +++ b/src/dynarmic/common/u128.h @@ -8,8 +8,9 @@ #include #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include namespace Dynarmic { @@ -27,7 +28,7 @@ struct u128 { /* implicit */ u128(T value) : lower(value), upper(0) { static_assert(std::is_integral_v); - static_assert(Common::BitSize() <= Common::BitSize()); + static_assert(mcl::bitsizeof <= mcl::bitsizeof); } u64 lower = 0; @@ -37,14 +38,14 @@ struct u128 { bool Bit() const { static_assert(bit_position < 128); if constexpr (bit_position < 64) { - return Common::Bit(lower); + return mcl::bit::get_bit(lower); } else { - return Common::Bit(upper); + return mcl::bit::get_bit(upper); } } }; -static_assert(Common::BitSize() == 128); +static_assert(mcl::bitsizeof == 128); static_assert(std::is_standard_layout_v); static_assert(std::is_trivially_copyable_v); diff --git a/src/dynarmic/common/unlikely.h b/src/dynarmic/common/unlikely.h deleted file mode 100644 index 746418da..00000000 --- a/src/dynarmic/common/unlikely.h +++ /dev/null @@ -1,12 +0,0 @@ -/* This file is part of the dynarmic project. - * Copyright (c) 2020 MerryMage - * SPDX-License-Identifier: 0BSD - */ - -#pragma once - -#if defined(__clang__) || defined(__GNUC__) -# define UNLIKELY(x) __builtin_expect(!!(x), 0) -#else -# define UNLIKELY(x) !!(x) -#endif diff --git a/src/dynarmic/common/x64_disassemble.cpp b/src/dynarmic/common/x64_disassemble.cpp index ce32028d..03d1d129 100644 --- a/src/dynarmic/common/x64_disassemble.cpp +++ b/src/dynarmic/common/x64_disassemble.cpp @@ -7,8 +7,7 @@ #include #include - -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/src/dynarmic/common/x64_disassemble.h b/src/dynarmic/common/x64_disassemble.h index ec7a3378..03c511bf 100644 --- a/src/dynarmic/common/x64_disassemble.h +++ b/src/dynarmic/common/x64_disassemble.h @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::Common { diff --git a/src/dynarmic/frontend/A32/FPSCR.h b/src/dynarmic/frontend/A32/FPSCR.h index f8f0205d..28414e9f 100644 --- a/src/dynarmic/frontend/A32/FPSCR.h +++ b/src/dynarmic/frontend/A32/FPSCR.h @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/fp/rounding_mode.h" namespace Dynarmic::A32 { @@ -33,52 +34,52 @@ public: /// Negative condition flag. bool N() const { - return Common::Bit<31>(value); + return mcl::bit::get_bit<31>(value); } /// Zero condition flag. bool Z() const { - return Common::Bit<30>(value); + return mcl::bit::get_bit<30>(value); } /// Carry condition flag. bool C() const { - return Common::Bit<29>(value); + return mcl::bit::get_bit<29>(value); } /// Overflow condition flag. bool V() const { - return Common::Bit<28>(value); + return mcl::bit::get_bit<28>(value); } /// Cumulative saturation flag. bool QC() const { - return Common::Bit<27>(value); + return mcl::bit::get_bit<27>(value); } /// Alternate half-precision control flag. bool AHP() const { - return Common::Bit<26>(value); + return mcl::bit::get_bit<26>(value); } /// Default NaN mode control bit. bool DN() const { - return Common::Bit<25>(value); + return mcl::bit::get_bit<25>(value); } /// Flush-to-zero mode control bit. bool FTZ() const { - return Common::Bit<24>(value); + return mcl::bit::get_bit<24>(value); } /// Rounding mode control field. FP::RoundingMode RMode() const { - return static_cast(Common::Bits<22, 23>(value)); + return static_cast(mcl::bit::get_bits<22, 23>(value)); } /// Indicates the stride of a vector. std::optional Stride() const { - switch (Common::Bits<20, 21>(value)) { + switch (mcl::bit::get_bits<20, 21>(value)) { case 0b00: return 1; case 0b11: @@ -90,67 +91,67 @@ public: /// Indicates the length of a vector. size_t Len() const { - return Common::Bits<16, 18>(value) + 1; + return mcl::bit::get_bits<16, 18>(value) + 1; } /// Input denormal exception trap enable flag. bool IDE() const { - return Common::Bit<15>(value); + return mcl::bit::get_bit<15>(value); } /// Inexact exception trap enable flag. bool IXE() const { - return Common::Bit<12>(value); + return mcl::bit::get_bit<12>(value); } /// Underflow exception trap enable flag. bool UFE() const { - return Common::Bit<11>(value); + return mcl::bit::get_bit<11>(value); } /// Overflow exception trap enable flag. bool OFE() const { - return Common::Bit<10>(value); + return mcl::bit::get_bit<10>(value); } /// Division by zero exception trap enable flag. bool DZE() const { - return Common::Bit<9>(value); + return mcl::bit::get_bit<9>(value); } /// Invalid operation exception trap enable flag. bool IOE() const { - return Common::Bit<8>(value); + return mcl::bit::get_bit<8>(value); } /// Input denormal cumulative exception bit. bool IDC() const { - return Common::Bit<7>(value); + return mcl::bit::get_bit<7>(value); } /// Inexact cumulative exception bit. bool IXC() const { - return Common::Bit<4>(value); + return mcl::bit::get_bit<4>(value); } /// Underflow cumulative exception bit. bool UFC() const { - return Common::Bit<3>(value); + return mcl::bit::get_bit<3>(value); } /// Overflow cumulative exception bit. bool OFC() const { - return Common::Bit<2>(value); + return mcl::bit::get_bit<2>(value); } /// Division by zero cumulative exception bit. bool DZC() const { - return Common::Bit<1>(value); + return mcl::bit::get_bit<1>(value); } /// Invalid operation cumulative exception bit. bool IOC() const { - return Common::Bit<0>(value); + return mcl::bit::get_bit<0>(value); } /** diff --git a/src/dynarmic/frontend/A32/ITState.h b/src/dynarmic/frontend/A32/ITState.h index ef8228f1..ae69fa1e 100644 --- a/src/dynarmic/frontend/A32/ITState.h +++ b/src/dynarmic/frontend/A32/ITState.h @@ -5,8 +5,9 @@ #pragma once -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/ir/cond.h" namespace Dynarmic::A32 { @@ -26,22 +27,22 @@ public: if (value == 0b00000000) { return IR::Cond::AL; } - return static_cast(Common::Bits<4, 7>(value)); + return static_cast(mcl::bit::get_bits<4, 7>(value)); } bool IsInITBlock() const { - return Common::Bits<0, 3>(value) != 0b0000; + return mcl::bit::get_bits<0, 3>(value) != 0b0000; } bool IsLastInITBlock() const { - return Common::Bits<0, 3>(value) == 0b1000; + return mcl::bit::get_bits<0, 3>(value) == 0b1000; } ITState Advance() const { - if (Common::Bits<0, 2>(value) == 0b000) { + if (mcl::bit::get_bits<0, 2>(value) == 0b000) { return ITState{0b00000000}; } - return ITState{Common::ModifyBits<0, 4>(value, static_cast(Common::Bits<0, 4>(value) << 1))}; + return ITState{mcl::bit::set_bits<0, 4>(value, static_cast(mcl::bit::get_bits<0, 4>(value) << 1))}; } u8 Value() const { diff --git a/src/dynarmic/frontend/A32/PSR.h b/src/dynarmic/frontend/A32/PSR.h index 5c12ba4b..9af78eaa 100644 --- a/src/dynarmic/frontend/A32/PSR.h +++ b/src/dynarmic/frontend/A32/PSR.h @@ -5,8 +5,9 @@ #pragma once -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/frontend/A32/ITState.h" namespace Dynarmic::A32 { @@ -65,52 +66,52 @@ public: } bool N() const { - return Common::Bit<31>(value); + return mcl::bit::get_bit<31>(value); } void N(bool set) { - value = Common::ModifyBit<31>(value, set); + value = mcl::bit::set_bit<31>(value, set); } bool Z() const { - return Common::Bit<30>(value); + return mcl::bit::get_bit<30>(value); } void Z(bool set) { - value = Common::ModifyBit<30>(value, set); + value = mcl::bit::set_bit<30>(value, set); } bool C() const { - return Common::Bit<29>(value); + return mcl::bit::get_bit<29>(value); } void C(bool set) { - value = Common::ModifyBit<29>(value, set); + value = mcl::bit::set_bit<29>(value, set); } bool V() const { - return Common::Bit<28>(value); + return mcl::bit::get_bit<28>(value); } void V(bool set) { - value = Common::ModifyBit<28>(value, set); + value = mcl::bit::set_bit<28>(value, set); } bool Q() const { - return Common::Bit<27>(value); + return mcl::bit::get_bit<27>(value); } void Q(bool set) { - value = Common::ModifyBit<27>(value, set); + value = mcl::bit::set_bit<27>(value, set); } bool J() const { - return Common::Bit<24>(value); + return mcl::bit::get_bit<24>(value); } void J(bool set) { - value = Common::ModifyBit<24>(value, set); + value = mcl::bit::set_bit<24>(value, set); } u32 GE() const { - return Common::Bits<16, 19>(value); + return mcl::bit::get_bits<16, 19>(value); } void GE(u32 data) { - value = Common::ModifyBits<16, 19>(value, data); + value = mcl::bit::set_bits<16, 19>(value, data); } ITState IT() const { @@ -123,45 +124,45 @@ public: } bool E() const { - return Common::Bit<9>(value); + return mcl::bit::get_bit<9>(value); } void E(bool set) { - value = Common::ModifyBit<9>(value, set); + value = mcl::bit::set_bit<9>(value, set); } bool A() const { - return Common::Bit<8>(value); + return mcl::bit::get_bit<8>(value); } void A(bool set) { - value = Common::ModifyBit<8>(value, set); + value = mcl::bit::set_bit<8>(value, set); } bool I() const { - return Common::Bit<7>(value); + return mcl::bit::get_bit<7>(value); } void I(bool set) { - value = Common::ModifyBit<7>(value, set); + value = mcl::bit::set_bit<7>(value, set); } bool F() const { - return Common::Bit<6>(value); + return mcl::bit::get_bit<6>(value); } void F(bool set) { - value = Common::ModifyBit<6>(value, set); + value = mcl::bit::set_bit<6>(value, set); } bool T() const { - return Common::Bit<5>(value); + return mcl::bit::get_bit<5>(value); } void T(bool set) { - value = Common::ModifyBit<5>(value, set); + value = mcl::bit::set_bit<5>(value, set); } Mode M() const { - return static_cast(Common::Bits<0, 4>(value)); + return static_cast(mcl::bit::get_bits<0, 4>(value)); } void M(Mode mode) { - value = Common::ModifyBits<0, 4>(value, static_cast(mode)); + value = mcl::bit::set_bits<0, 4>(value, static_cast(mode)); } u32 Value() const { diff --git a/src/dynarmic/frontend/A32/a32_ir_emitter.cpp b/src/dynarmic/frontend/A32/a32_ir_emitter.cpp index 8d2b9db7..9b9e645d 100644 --- a/src/dynarmic/frontend/A32/a32_ir_emitter.cpp +++ b/src/dynarmic/frontend/A32/a32_ir_emitter.cpp @@ -5,7 +5,8 @@ #include "dynarmic/frontend/A32/a32_ir_emitter.h" -#include "dynarmic/common/assert.h" +#include + #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/interface/A32/arch_version.h" #include "dynarmic/ir/opcodes.h" diff --git a/src/dynarmic/frontend/A32/a32_ir_emitter.h b/src/dynarmic/frontend/A32/a32_ir_emitter.h index 0f36958a..8cdebe49 100644 --- a/src/dynarmic/frontend/A32/a32_ir_emitter.h +++ b/src/dynarmic/frontend/A32/a32_ir_emitter.h @@ -7,7 +7,8 @@ #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/ir/ir_emitter.h" #include "dynarmic/ir/value.h" diff --git a/src/dynarmic/frontend/A32/a32_location_descriptor.h b/src/dynarmic/frontend/A32/a32_location_descriptor.h index 4b68d2de..3bdb72c9 100644 --- a/src/dynarmic/frontend/A32/a32_location_descriptor.h +++ b/src/dynarmic/frontend/A32/a32_location_descriptor.h @@ -9,7 +9,8 @@ #include #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/A32/FPSCR.h" #include "dynarmic/frontend/A32/ITState.h" #include "dynarmic/frontend/A32/PSR.h" diff --git a/src/dynarmic/frontend/A32/a32_types.cpp b/src/dynarmic/frontend/A32/a32_types.cpp index 04628627..c922f57b 100644 --- a/src/dynarmic/frontend/A32/a32_types.cpp +++ b/src/dynarmic/frontend/A32/a32_types.cpp @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/bit_util.h" +#include namespace Dynarmic::A32 { @@ -46,7 +46,7 @@ std::string RegListToString(RegList reg_list) { std::string ret; bool first_reg = true; for (size_t i = 0; i < 16; i++) { - if (Common::Bit(i, reg_list)) { + if (mcl::bit::get_bit(i, reg_list)) { if (!first_reg) { ret += ", "; } diff --git a/src/dynarmic/frontend/A32/a32_types.h b/src/dynarmic/frontend/A32/a32_types.h index ff30cc76..5d1166f3 100644 --- a/src/dynarmic/frontend/A32/a32_types.h +++ b/src/dynarmic/frontend/A32/a32_types.h @@ -9,8 +9,9 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/interface/A32/coprocessor_util.h" #include "dynarmic/ir/cond.h" diff --git a/src/dynarmic/frontend/A32/decoder/arm.h b/src/dynarmic/frontend/A32/decoder/arm.h index 3ef69c05..5b4a7b34 100644 --- a/src/dynarmic/frontend/A32/decoder/arm.h +++ b/src/dynarmic/frontend/A32/decoder/arm.h @@ -12,8 +12,9 @@ #include #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" @@ -34,7 +35,7 @@ std::vector> GetArmDecodeTable() { // If a matcher has more bits in its mask it is more specific, so it should come first. std::stable_sort(table.begin(), table.end(), [](const auto& matcher1, const auto& matcher2) { - return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask()); + return mcl::bit::count_ones(matcher1.GetMask()) > mcl::bit::count_ones(matcher2.GetMask()); }); return table; diff --git a/src/dynarmic/frontend/A32/decoder/asimd.h b/src/dynarmic/frontend/A32/decoder/asimd.h index 73b02975..cfcd28c6 100644 --- a/src/dynarmic/frontend/A32/decoder/asimd.h +++ b/src/dynarmic/frontend/A32/decoder/asimd.h @@ -11,8 +11,9 @@ #include #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" @@ -58,7 +59,7 @@ std::vector> GetASIMDDecodeTable() { // If a matcher has more bits in its mask it is more specific, so it should come first. std::stable_sort(sort_begin, sort_end, [](const auto& matcher1, const auto& matcher2) { - return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask()); + return mcl::bit::count_ones(matcher1.GetMask()) > mcl::bit::count_ones(matcher2.GetMask()); }); return table; diff --git a/src/dynarmic/frontend/A32/decoder/thumb16.h b/src/dynarmic/frontend/A32/decoder/thumb16.h index 568d5f42..6a4275f7 100644 --- a/src/dynarmic/frontend/A32/decoder/thumb16.h +++ b/src/dynarmic/frontend/A32/decoder/thumb16.h @@ -10,7 +10,8 @@ #include #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/src/dynarmic/frontend/A32/decoder/thumb32.h b/src/dynarmic/frontend/A32/decoder/thumb32.h index 2d5d5b1e..f3f4b3b9 100644 --- a/src/dynarmic/frontend/A32/decoder/thumb32.h +++ b/src/dynarmic/frontend/A32/decoder/thumb32.h @@ -9,7 +9,8 @@ #include #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/src/dynarmic/frontend/A32/decoder/vfp.h b/src/dynarmic/frontend/A32/decoder/vfp.h index 62b1288a..f79a859b 100644 --- a/src/dynarmic/frontend/A32/decoder/vfp.h +++ b/src/dynarmic/frontend/A32/decoder/vfp.h @@ -10,7 +10,8 @@ #include #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" diff --git a/src/dynarmic/frontend/A32/disassembler/disassembler.h b/src/dynarmic/frontend/A32/disassembler/disassembler.h index 65dac998..6a61afde 100644 --- a/src/dynarmic/frontend/A32/disassembler/disassembler.h +++ b/src/dynarmic/frontend/A32/disassembler/disassembler.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::A32 { diff --git a/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp b/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp index b42600dc..ff0c48a1 100644 --- a/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp +++ b/src/dynarmic/frontend/A32/disassembler/disassembler_arm.cpp @@ -8,8 +8,9 @@ #include #include +#include +#include -#include "dynarmic/common/bit_util.h" #include "dynarmic/common/string_util.h" #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/frontend/A32/decoder/arm.h" @@ -24,7 +25,7 @@ public: using instruction_return_type = std::string; static u32 ArmExpandImm(int rotate, Imm<8> imm8) { - return Common::RotateRight(static_cast(imm8.ZeroExtend()), rotate * 2); + return mcl::bit::rotate_right(static_cast(imm8.ZeroExtend()), rotate * 2); } static std::string ShiftStr(ShiftType shift, Imm<5> imm5) { @@ -150,15 +151,15 @@ public: // Branch instructions std::string arm_B(Cond cond, Imm<24> imm24) { - const s32 offset = Common::SignExtend<26, s32>(imm24.ZeroExtend() << 2) + 8; + const s32 offset = static_cast(mcl::bit::sign_extend<26, u32>(imm24.ZeroExtend() << 2) + 8); return fmt::format("b{} {}#{}", CondToString(cond), Common::SignToChar(offset), abs(offset)); } std::string arm_BL(Cond cond, Imm<24> imm24) { - const s32 offset = Common::SignExtend<26, s32>(imm24.ZeroExtend() << 2) + 8; + const s32 offset = static_cast(mcl::bit::sign_extend<26, u32>(imm24.ZeroExtend() << 2) + 8); return fmt::format("bl{} {}#{}", CondToString(cond), Common::SignToChar(offset), abs(offset)); } std::string arm_BLX_imm(bool H, Imm<24> imm24) { - const s32 offset = Common::SignExtend<26, s32>(imm24.ZeroExtend() << 2) + 8 + (H ? 2 : 0); + const s32 offset = static_cast(mcl::bit::sign_extend<26, u32>(imm24.ZeroExtend() << 2) + 8 + (H ? 2 : 0)); return fmt::format("blx {}#{}", Common::SignToChar(offset), abs(offset)); } std::string arm_BLX_reg(Cond cond, Reg m) { @@ -1209,11 +1210,11 @@ public: std::string arm_MRS(Cond cond, Reg d) { return fmt::format("mrs{} {}, apsr", CondToString(cond), d); } - std::string arm_MSR_imm(Cond cond, int mask, int rotate, Imm<8> imm8) { - const bool write_c = Common::Bit<0>(mask); - const bool write_x = Common::Bit<1>(mask); - const bool write_s = Common::Bit<2>(mask); - const bool write_f = Common::Bit<3>(mask); + std::string arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8) { + const bool write_c = mcl::bit::get_bit<0>(mask); + const bool write_x = mcl::bit::get_bit<1>(mask); + const bool write_s = mcl::bit::get_bit<2>(mask); + const bool write_f = mcl::bit::get_bit<3>(mask); return fmt::format("msr{} cpsr_{}{}{}{}, #{}", CondToString(cond), write_c ? "c" : "", @@ -1222,11 +1223,11 @@ public: write_f ? "f" : "", ArmExpandImm(rotate, imm8)); } - std::string arm_MSR_reg(Cond cond, int mask, Reg n) { - const bool write_c = Common::Bit<0>(mask); - const bool write_x = Common::Bit<1>(mask); - const bool write_s = Common::Bit<2>(mask); - const bool write_f = Common::Bit<3>(mask); + std::string arm_MSR_reg(Cond cond, unsigned mask, Reg n) { + const bool write_c = mcl::bit::get_bit<0>(mask); + const bool write_x = mcl::bit::get_bit<1>(mask); + const bool write_s = mcl::bit::get_bit<2>(mask); + const bool write_f = mcl::bit::get_bit<3>(mask); return fmt::format("msr{} cpsr_{}{}{}{}, {}", CondToString(cond), write_c ? "c" : "", diff --git a/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp b/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp index ec05b0dd..86018131 100644 --- a/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp +++ b/src/dynarmic/frontend/A32/disassembler/disassembler_thumb.cpp @@ -8,8 +8,8 @@ #include #include +#include -#include "dynarmic/common/bit_util.h" #include "dynarmic/common/string_util.h" #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/frontend/A32/decoder/thumb16.h" @@ -345,7 +345,7 @@ public: } std::string thumb16_LDMIA(Reg n, RegList reg_list) { - const bool write_back = !Common::Bit(static_cast(n), reg_list); + const bool write_back = !mcl::bit::get_bit(static_cast(n), reg_list); return fmt::format("ldm {}{}, {{{}}}", n, write_back ? "!" : "", RegListToString(reg_list)); } diff --git a/src/dynarmic/frontend/A32/translate/a32_translate.h b/src/dynarmic/frontend/A32/translate/a32_translate.h index 9af458e6..0f2c3a12 100644 --- a/src/dynarmic/frontend/A32/translate/a32_translate.h +++ b/src/dynarmic/frontend/A32/translate/a32_translate.h @@ -4,7 +4,8 @@ */ #pragma once -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/interface/A32/arch_version.h" namespace Dynarmic::IR { diff --git a/src/dynarmic/frontend/A32/translate/conditional_state.cpp b/src/dynarmic/frontend/A32/translate/conditional_state.cpp index 9488e628..8bd875c7 100644 --- a/src/dynarmic/frontend/A32/translate/conditional_state.cpp +++ b/src/dynarmic/frontend/A32/translate/conditional_state.cpp @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/frontend/A32/a32_ir_emitter.h" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" #include "dynarmic/interface/A32/config.h" diff --git a/src/dynarmic/frontend/A32/translate/conditional_state.h b/src/dynarmic/frontend/A32/translate/conditional_state.h index a86bf9fb..18c8b1cc 100644 --- a/src/dynarmic/frontend/A32/translate/conditional_state.h +++ b/src/dynarmic/frontend/A32/translate/conditional_state.h @@ -5,7 +5,7 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { enum class Cond; diff --git a/src/dynarmic/frontend/A32/translate/impl/a32_branch.cpp b/src/dynarmic/frontend/A32/translate/impl/a32_branch.cpp index 41beea7b..d87cfcfe 100644 --- a/src/dynarmic/frontend/A32/translate/impl/a32_branch.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/a32_branch.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -14,7 +15,7 @@ bool TranslatorVisitor::arm_B(Cond cond, Imm<24> imm24) { return true; } - const u32 imm32 = Common::SignExtend<26, u32>(imm24.ZeroExtend() << 2) + 8; + const u32 imm32 = mcl::bit::sign_extend<26, u32>(imm24.ZeroExtend() << 2) + 8; const auto new_location = ir.current_location.AdvancePC(imm32); ir.SetTerm(IR::Term::LinkBlock{new_location}); return false; @@ -29,7 +30,7 @@ bool TranslatorVisitor::arm_BL(Cond cond, Imm<24> imm24) { ir.PushRSB(ir.current_location.AdvancePC(4)); ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4)); - const u32 imm32 = Common::SignExtend<26, u32>(imm24.ZeroExtend() << 2) + 8; + const u32 imm32 = mcl::bit::sign_extend<26, u32>(imm24.ZeroExtend() << 2) + 8; const auto new_location = ir.current_location.AdvancePC(imm32); ir.SetTerm(IR::Term::LinkBlock{new_location}); return false; @@ -40,7 +41,7 @@ bool TranslatorVisitor::arm_BLX_imm(bool H, Imm<24> imm24) { ir.PushRSB(ir.current_location.AdvancePC(4)); ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4)); - const u32 imm32 = Common::SignExtend<26, u32>((imm24.ZeroExtend() << 2)) + (H ? 2 : 0) + 8; + const u32 imm32 = mcl::bit::sign_extend<26, u32>((imm24.ZeroExtend() << 2)) + (H ? 2 : 0) + 8; const auto new_location = ir.current_location.AdvancePC(imm32).SetTFlag(true); ir.SetTerm(IR::Term::LinkBlock{new_location}); return false; diff --git a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp index e85231a4..276f8384 100644 --- a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp @@ -5,7 +5,8 @@ #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" -#include "dynarmic/common/assert.h" +#include + #include "dynarmic/interface/A32/config.h" namespace Dynarmic::A32 { diff --git a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h index d20a2c56..61a97b1c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h +++ b/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.h @@ -5,8 +5,10 @@ #pragma once -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include +#include + #include "dynarmic/frontend/A32/a32_ir_emitter.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" @@ -49,8 +51,8 @@ struct TranslatorVisitor final { u32 imm32 = imm8.ZeroExtend(); auto carry_out = carry_in; if (rotate) { - imm32 = Common::RotateRight(imm8.ZeroExtend(), rotate * 2); - carry_out = ir.Imm1(Common::Bit<31>(imm32)); + imm32 = mcl::bit::rotate_right(imm8.ZeroExtend(), rotate * 2); + carry_out = ir.Imm1(mcl::bit::get_bit<31>(imm32)); } return {imm32, carry_out}; } @@ -68,18 +70,18 @@ struct TranslatorVisitor final { case 0b00: return imm8; case 0b01: - return Common::Replicate(imm8, 16); + return mcl::bit::replicate_element(imm8); case 0b10: - return Common::Replicate(imm8 << 8, 16); + return mcl::bit::replicate_element(imm8 << 8); case 0b11: - return Common::Replicate(imm8, 8); + return mcl::bit::replicate_element(imm8); } UNREACHABLE(); }(); return {imm32, carry_in}; } - const u32 imm32 = Common::RotateRight((1 << 7) | imm12.Bits<0, 6>(), imm12.Bits<7, 11>()); - return {imm32, ir.Imm1(Common::Bit<31>(imm32))}; + const u32 imm32 = mcl::bit::rotate_right((1 << 7) | imm12.Bits<0, 6>(), imm12.Bits<7, 11>()); + return {imm32, ir.Imm1(mcl::bit::get_bit<31>(imm32))}; } u32 ThumbExpandImm(Imm<1> i, Imm<3> imm3, Imm<8> imm8) { @@ -397,8 +399,8 @@ struct TranslatorVisitor final { // Status register access instructions bool arm_CPS(); bool arm_MRS(Cond cond, Reg d); - bool arm_MSR_imm(Cond cond, int mask, int rotate, Imm<8> imm8); - bool arm_MSR_reg(Cond cond, int mask, Reg n); + bool arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8); + bool arm_MSR_reg(Cond cond, unsigned mask, Reg n); bool arm_RFE(); bool arm_SETEND(bool E); bool arm_SRS(); diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp index 4afd0b1f..d444e023 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp @@ -6,7 +6,8 @@ #include #include -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -16,7 +17,7 @@ namespace { std::optional> DecodeType(Imm<4> type, size_t size, size_t align) { switch (type.ZeroExtend()) { case 0b0111: // VST1 A1 / VLD1 A1 - if (Common::Bit<1>(align)) { + if (mcl::bit::get_bit<1>(align)) { return std::nullopt; } return std::tuple{1, 1, 0}; @@ -26,7 +27,7 @@ std::optional> DecodeType(Imm<4> type, size_t } return std::tuple{1, 2, 0}; case 0b0110: // VST1 A3 / VLD1 A3 - if (Common::Bit<1>(align)) { + if (mcl::bit::get_bit<1>(align)) { return std::nullopt; } return std::tuple{1, 3, 0}; @@ -48,12 +49,12 @@ std::optional> DecodeType(Imm<4> type, size_t } return std::tuple{2, 2, 2}; case 0b0100: // VST3 / VLD3 - if (size == 0b11 || Common::Bit<1>(align)) { + if (size == 0b11 || mcl::bit::get_bit<1>(align)) { return std::nullopt; } return std::tuple{3, 1, 1}; case 0b0101: // VST3 / VLD3 - if (size == 0b11 || Common::Bit<1>(align)) { + if (size == 0b11 || mcl::bit::get_bit<1>(align)) { return std::nullopt; } return std::tuple{3, 1, 2}; @@ -250,14 +251,14 @@ bool TranslatorVisitor::v8_VST_single(bool D, Reg n, size_t Vd, size_t sz, size_ return DecodeError(); } - if (nelem == 1 && Common::Bit(sz, index_align)) { + if (nelem == 1 && mcl::bit::get_bit(sz, index_align)) { return UndefinedInstruction(); } const size_t ebytes = size_t(1) << sz; - const size_t index = Common::Bits(sz + 1, 3, index_align); - const size_t inc = (sz != 0 && Common::Bit(sz, index_align)) ? 2 : 1; - const size_t a = Common::Bits(0, sz ? sz - 1 : 0, index_align); + const size_t index = mcl::bit::get_bits(sz + 1, 3, index_align); + const size_t inc = (sz != 0 && mcl::bit::get_bit(sz, index_align)) ? 2 : 1; + const size_t a = mcl::bit::get_bits(0, sz ? sz - 1 : 0, index_align); if (nelem == 1 && inc == 2) { return UndefinedInstruction(); @@ -265,7 +266,7 @@ bool TranslatorVisitor::v8_VST_single(bool D, Reg n, size_t Vd, size_t sz, size_ if (nelem == 1 && sz == 2 && (a != 0b00 && a != 0b11)) { return UndefinedInstruction(); } - if (nelem == 2 && Common::Bit<1>(a)) { + if (nelem == 2 && mcl::bit::get_bit<1>(a)) { return UndefinedInstruction(); } if (nelem == 3 && a != 0b00) { @@ -314,14 +315,14 @@ bool TranslatorVisitor::v8_VLD_single(bool D, Reg n, size_t Vd, size_t sz, size_ return DecodeError(); } - if (nelem == 1 && Common::Bit(sz, index_align)) { + if (nelem == 1 && mcl::bit::get_bit(sz, index_align)) { return UndefinedInstruction(); } const size_t ebytes = size_t(1) << sz; - const size_t index = Common::Bits(sz + 1, 3, index_align); - const size_t inc = (sz != 0 && Common::Bit(sz, index_align)) ? 2 : 1; - const size_t a = Common::Bits(0, sz ? sz - 1 : 0, index_align); + const size_t index = mcl::bit::get_bits(sz + 1, 3, index_align); + const size_t inc = (sz != 0 && mcl::bit::get_bit(sz, index_align)) ? 2 : 1; + const size_t a = mcl::bit::get_bits(0, sz ? sz - 1 : 0, index_align); if (nelem == 1 && inc == 2) { return UndefinedInstruction(); @@ -329,7 +330,7 @@ bool TranslatorVisitor::v8_VLD_single(bool D, Reg n, size_t Vd, size_t sz, size_ if (nelem == 1 && sz == 2 && (a != 0b00 && a != 0b11)) { return UndefinedInstruction(); } - if (nelem == 2 && Common::Bit<1>(a)) { + if (nelem == 2 && mcl::bit::get_bit<1>(a)) { return UndefinedInstruction(); } if (nelem == 3 && a != 0b00) { diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp index aae0018b..1dcab279 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_misc.cpp @@ -3,8 +3,10 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -35,7 +37,7 @@ static bool TableLookup(TranslatorVisitor& v, bool is_vtbl, bool D, size_t Vn, s } bool TranslatorVisitor::asimd_VEXT(bool D, size_t Vn, size_t Vd, Imm<4> imm4, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -65,7 +67,7 @@ bool TranslatorVisitor::asimd_VTBX(bool D, size_t Vn, size_t Vd, size_t len, boo } bool TranslatorVisitor::asimd_VDUP_scalar(bool D, Imm<4> imm4, size_t Vd, bool Q, bool M, size_t Vm) { - if (Q && Common::Bit<0>(Vd)) { + if (Q && mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } @@ -73,7 +75,7 @@ bool TranslatorVisitor::asimd_VDUP_scalar(bool D, Imm<4> imm4, size_t Vd, bool Q return UndefinedInstruction(); } - const size_t imm4_lsb = Common::LowestSetBit(imm4.ZeroExtend()); + const size_t imm4_lsb = mcl::bit::lowest_set_bit(imm4.ZeroExtend()); const size_t esize = 8u << imm4_lsb; const size_t index = imm4.ZeroExtend() >> (imm4_lsb + 1); const auto d = ToVector(Q, Vd, D); diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp index a0fda631..7427770c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_one_reg_modified_immediate.cpp @@ -3,14 +3,15 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { bool TranslatorVisitor::asimd_VMOV_imm(Imm<1> a, bool D, Imm<1> b, Imm<1> c, Imm<1> d, size_t Vd, Imm<4> cmode, bool Q, bool op, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h) { - if (Q && Common::Bit<0>(Vd)) { + if (Q && mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp index f803d059..bf7abde2 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_three_regs.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -28,7 +29,7 @@ enum class WidenBehaviour { template bool BitwiseInstruction(TranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -54,7 +55,7 @@ bool BitwiseInstruction(TranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool template bool FloatingPointInstruction(TranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -80,7 +81,7 @@ bool IntegerComparison(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t V return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -115,7 +116,7 @@ bool FloatComparison(TranslatorVisitor& v, bool D, bool sz, size_t Vn, size_t Vd return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -151,7 +152,7 @@ bool AbsoluteDifference(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -183,7 +184,7 @@ bool AbsoluteDifferenceLong(TranslatorVisitor& v, bool U, bool D, size_t sz, siz return v.DecodeError(); } - if (Common::Bit<0>(Vd)) { + if (mcl::bit::get_bit<0>(Vd)) { return v.UndefinedInstruction(); } @@ -221,7 +222,7 @@ bool WideInstruction(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, return v.DecodeError(); } - if (Common::Bit<0>(Vd) || (!widen_first && Common::Bit<0>(Vn))) { + if (mcl::bit::get_bit<0>(Vd) || (!widen_first && mcl::bit::get_bit<0>(Vn))) { return v.UndefinedInstruction(); } @@ -245,7 +246,7 @@ bool WideInstruction(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t Vn, // ASIMD Three registers of the same length bool TranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -267,7 +268,7 @@ bool TranslatorVisitor::asimd_VHADD(bool U, bool D, size_t sz, size_t Vn, size_t } bool TranslatorVisitor::asimd_VQADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -289,7 +290,7 @@ bool TranslatorVisitor::asimd_VQADD(bool U, bool D, size_t sz, size_t Vn, size_t } bool TranslatorVisitor::asimd_VRHADD(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -359,7 +360,7 @@ bool TranslatorVisitor::asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, } bool TranslatorVisitor::asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -381,7 +382,7 @@ bool TranslatorVisitor::asimd_VHSUB(bool U, bool D, size_t sz, size_t Vn, size_t } bool TranslatorVisitor::asimd_VQSUB(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -419,7 +420,7 @@ bool TranslatorVisitor::asimd_VABA(bool U, bool D, size_t sz, size_t Vn, size_t } bool TranslatorVisitor::asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -437,7 +438,7 @@ bool TranslatorVisitor::asimd_VADD_int(bool D, size_t sz, size_t Vn, size_t Vd, } bool TranslatorVisitor::asimd_VSUB_int(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -455,7 +456,7 @@ bool TranslatorVisitor::asimd_VSUB_int(bool D, size_t sz, size_t Vn, size_t Vd, } bool TranslatorVisitor::asimd_VSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -474,7 +475,7 @@ bool TranslatorVisitor::asimd_VSHL_reg(bool U, bool D, size_t sz, size_t Vn, siz } bool TranslatorVisitor::asimd_VQSHL_reg(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -493,7 +494,7 @@ bool TranslatorVisitor::asimd_VQSHL_reg(bool U, bool D, size_t sz, size_t Vn, si } bool TranslatorVisitor::asimd_VRSHL(bool U, bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -516,7 +517,7 @@ bool TranslatorVisitor::asimd_VMAX(bool U, bool D, size_t sz, size_t Vn, size_t return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -542,7 +543,7 @@ bool TranslatorVisitor::asimd_VMAX(bool U, bool D, size_t sz, size_t Vn, size_t } bool TranslatorVisitor::asimd_VTST(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -573,7 +574,7 @@ bool TranslatorVisitor::asimd_VMLA(bool op, bool D, size_t sz, size_t Vn, size_t return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -598,7 +599,7 @@ bool TranslatorVisitor::asimd_VMUL(bool P, bool D, size_t sz, size_t Vn, size_t return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -647,7 +648,7 @@ bool TranslatorVisitor::asimd_VPMAX_int(bool U, bool D, size_t sz, size_t Vn, si } bool TranslatorVisitor::asimd_VQDMULH(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -669,7 +670,7 @@ bool TranslatorVisitor::asimd_VQDMULH(bool D, size_t sz, size_t Vn, size_t Vd, b } bool TranslatorVisitor::asimd_VQRDMULH(bool D, size_t sz, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -832,7 +833,7 @@ bool TranslatorVisitor::asimd_VRSQRTS(bool D, bool sz, size_t Vn, size_t Vd, boo } bool TranslatorVisitor::v8_SHA256H(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (!Q || Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm)) { + if (!Q || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -850,7 +851,7 @@ bool TranslatorVisitor::v8_SHA256H(bool D, size_t Vn, size_t Vd, bool N, bool Q, } bool TranslatorVisitor::v8_SHA256H2(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (!Q || Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm)) { + if (!Q || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -868,7 +869,7 @@ bool TranslatorVisitor::v8_SHA256H2(bool D, size_t Vn, size_t Vd, bool N, bool Q } bool TranslatorVisitor::v8_SHA256SU1(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) { - if (!Q || Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm)) { + if (!Q || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -920,7 +921,7 @@ bool TranslatorVisitor::asimd_VMULL(bool U, bool D, size_t sz, size_t Vn, size_t return DecodeError(); } - if ((P & (U || sz == 0b10)) || Common::Bit<0>(Vd)) { + if ((P & (U || sz == 0b10)) || mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp index e9532aa8..b1961b20 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_misc.cpp @@ -5,7 +5,8 @@ #include -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -23,7 +24,7 @@ bool CompareWithZero(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool F, return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -76,7 +77,7 @@ bool PairedAddOperation(TranslatorVisitor& v, bool D, size_t sz, size_t Vd, bool return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -108,7 +109,7 @@ bool TranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -168,7 +169,7 @@ bool TranslatorVisitor::asimd_VPADDL(bool D, size_t sz, size_t Vd, bool op, bool } bool TranslatorVisitor::v8_AESD(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + if (sz != 0b00 || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -183,7 +184,7 @@ bool TranslatorVisitor::v8_AESD(bool D, size_t sz, size_t Vd, bool M, size_t Vm) } bool TranslatorVisitor::v8_AESE(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + if (sz != 0b00 || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -198,7 +199,7 @@ bool TranslatorVisitor::v8_AESE(bool D, size_t sz, size_t Vd, bool M, size_t Vm) } bool TranslatorVisitor::v8_AESIMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + if (sz != 0b00 || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -212,7 +213,7 @@ bool TranslatorVisitor::v8_AESIMC(bool D, size_t sz, size_t Vd, bool M, size_t V } bool TranslatorVisitor::v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz != 0b00 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + if (sz != 0b00 || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -226,7 +227,7 @@ bool TranslatorVisitor::v8_AESMC(bool D, size_t sz, size_t Vd, bool M, size_t Vm } bool TranslatorVisitor::v8_SHA256SU0(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz != 0b10 || Common::Bit<0>(Vd) || Common::Bit<0>(Vm)) { + if (sz != 0b10 || mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -245,7 +246,7 @@ bool TranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -269,7 +270,7 @@ bool TranslatorVisitor::asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -291,7 +292,7 @@ bool TranslatorVisitor::asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -309,7 +310,7 @@ bool TranslatorVisitor::asimd_VMVN_reg(bool D, size_t sz, size_t Vd, bool Q, boo return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -332,7 +333,7 @@ bool TranslatorVisitor::asimd_VQABS(bool D, size_t sz, size_t Vd, bool Q, bool M return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -352,7 +353,7 @@ bool TranslatorVisitor::asimd_VQNEG(bool D, size_t sz, size_t Vd, bool Q, bool M return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -392,7 +393,7 @@ bool TranslatorVisitor::asimd_VABS(bool D, size_t sz, size_t Vd, bool F, bool Q, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -418,7 +419,7 @@ bool TranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -440,7 +441,7 @@ bool TranslatorVisitor::asimd_VNEG(bool D, size_t sz, size_t Vd, bool F, bool Q, } bool TranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -473,7 +474,7 @@ bool TranslatorVisitor::asimd_VTRN(bool D, size_t sz, size_t Vd, bool Q, bool M, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -500,7 +501,7 @@ bool TranslatorVisitor::asimd_VUZP(bool D, size_t sz, size_t Vd, bool Q, bool M, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -532,7 +533,7 @@ bool TranslatorVisitor::asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, return UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -563,7 +564,7 @@ bool TranslatorVisitor::asimd_VZIP(bool D, size_t sz, size_t Vd, bool Q, bool M, } bool TranslatorVisitor::asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz == 0b11 || Common::Bit<0>(Vm)) { + if (sz == 0b11 || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } const size_t esize = 8U << sz; @@ -578,7 +579,7 @@ bool TranslatorVisitor::asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t } bool TranslatorVisitor::asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz == 0b11 || Common::Bit<0>(Vm)) { + if (sz == 0b11 || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } const size_t esize = 8U << sz; @@ -593,7 +594,7 @@ bool TranslatorVisitor::asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size } bool TranslatorVisitor::asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool M, size_t Vm) { - if (sz == 0b11 || Common::Bit<0>(Vm)) { + if (sz == 0b11 || mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } const size_t esize = 8U << sz; @@ -609,7 +610,7 @@ bool TranslatorVisitor::asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool } bool TranslatorVisitor::asimd_VSHLL_max(bool D, size_t sz, size_t Vd, bool M, size_t Vm) { - if (sz == 0b11 || Common::Bit<0>(Vd)) { + if (sz == 0b11 || mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } const size_t esize = 8U << sz; @@ -627,10 +628,10 @@ bool TranslatorVisitor::asimd_VCVT_half(bool D, size_t sz, size_t Vd, bool half_ if (sz != 0b01) { return UndefinedInstruction(); } - if (half_to_single && Common::Bit<0>(Vd)) { + if (half_to_single && mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } - if (!half_to_single && Common::Bit<0>(Vm)) { + if (!half_to_single && mcl::bit::get_bit<0>(Vm)) { return UndefinedInstruction(); } @@ -647,7 +648,7 @@ bool TranslatorVisitor::asimd_VCVT_half(bool D, size_t sz, size_t Vd, bool half_ } bool TranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -673,7 +674,7 @@ bool TranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool } bool TranslatorVisitor::asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -699,7 +700,7 @@ bool TranslatorVisitor::asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool } bool TranslatorVisitor::asimd_VCVT_integer(bool D, size_t sz, size_t Vd, bool op, bool U, bool Q, bool M, size_t Vm) { - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp index 9b097965..4e774d41 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_scalar.cpp @@ -5,15 +5,16 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { namespace { std::pair GetScalarLocation(size_t esize, bool M, size_t Vm) { const ExtReg m = ExtReg::Q0 + ((Vm >> 1) & (esize == 16 ? 0b11 : 0b111)); - const size_t index = concatenate(Imm<1>{Common::Bit<0>(Vm)}, Imm<1>{M}, Imm<1>{Common::Bit<3>(Vm)}).ZeroExtend() >> (esize == 16 ? 0 : 1); + const size_t index = concatenate(Imm<1>{mcl::bit::get_bit<0>(Vm)}, Imm<1>{M}, Imm<1>{mcl::bit::get_bit<3>(Vm)}).ZeroExtend() >> (esize == 16 ? 0 : 1); return std::make_pair(m, index); } @@ -37,7 +38,7 @@ bool ScalarMultiply(TranslatorVisitor& v, bool Q, bool D, size_t sz, size_t Vn, return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn))) { return v.UndefinedInstruction(); } @@ -74,7 +75,7 @@ bool ScalarMultiplyLong(TranslatorVisitor& v, bool U, bool D, size_t sz, size_t return v.DecodeError(); } - if (sz == 0b00 || Common::Bit<0>(Vd)) { + if (sz == 0b00 || mcl::bit::get_bit<0>(Vd)) { return v.UndefinedInstruction(); } @@ -115,7 +116,7 @@ bool ScalarMultiplyReturnHigh(TranslatorVisitor& v, bool Q, bool D, size_t sz, s return v.UndefinedInstruction(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vn))) { return v.UndefinedInstruction(); } @@ -166,7 +167,7 @@ bool TranslatorVisitor::asimd_VQDMULL_scalar(bool D, size_t sz, size_t Vn, size_ return DecodeError(); } - if (sz == 0b00 || Common::Bit<0>(Vd)) { + if (sz == 0b00 || mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } diff --git a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp index f1d8e621..aec91d0c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/asimd_two_regs_shift.cpp @@ -3,8 +3,10 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -42,7 +44,7 @@ std::pair ElementSizeAndShiftAmount(bool right_shift, bool L, si return {64, 64 - imm6}; } - const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3); + const size_t esize = 8U << mcl::bit::highest_set_bit(imm6 >> 3); const size_t shift_amount = (esize * 2) - imm6; return {esize, shift_amount}; } else { @@ -50,18 +52,18 @@ std::pair ElementSizeAndShiftAmount(bool right_shift, bool L, si return {64, imm6}; } - const size_t esize = 8U << Common::HighestSetBit(imm6 >> 3); + const size_t esize = 8U << mcl::bit::highest_set_bit(imm6 >> 3); const size_t shift_amount = imm6 - esize; return {esize, shift_amount}; } } bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm, Accumulating accumulate, Rounding rounding) { - if (!L && Common::Bits<3, 5>(imm6) == 0) { + if (!L && mcl::bit::get_bits<3, 5>(imm6) == 0) { return v.DecodeError(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return v.UndefinedInstruction(); } @@ -88,11 +90,11 @@ bool ShiftRight(TranslatorVisitor& v, bool U, bool D, size_t imm6, size_t Vd, bo } bool ShiftRightNarrowing(TranslatorVisitor& v, bool D, size_t imm6, size_t Vd, bool M, size_t Vm, Rounding rounding, Narrowing narrowing, Signedness signedness) { - if (Common::Bits<3, 5>(imm6) == 0) { + if (mcl::bit::get_bits<3, 5>(imm6) == 0) { return v.DecodeError(); } - if (Common::Bit<0>(Vm)) { + if (mcl::bit::get_bit<0>(Vm)) { return v.UndefinedInstruction(); } @@ -158,16 +160,16 @@ bool TranslatorVisitor::asimd_VRSRA(bool U, bool D, size_t imm6, size_t Vd, bool } bool TranslatorVisitor::asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { - if (!L && Common::Bits<3, 5>(imm6) == 0) { + if (!L && mcl::bit::get_bits<3, 5>(imm6) == 0) { return DecodeError(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } const auto [esize, shift_amount] = ElementSizeAndShiftAmount(true, L, imm6); - const u64 mask = shift_amount == esize ? 0 : Common::Ones(esize) >> shift_amount; + const u64 mask = shift_amount == esize ? 0 : mcl::bit::ones(esize) >> shift_amount; const auto d = ToVector(Q, Vd, D); const auto m = ToVector(Q, Vm, M); @@ -184,16 +186,16 @@ bool TranslatorVisitor::asimd_VSRI(bool D, size_t imm6, size_t Vd, bool L, bool } bool TranslatorVisitor::asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { - if (!L && Common::Bits<3, 5>(imm6) == 0) { + if (!L && mcl::bit::get_bits<3, 5>(imm6) == 0) { return DecodeError(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, L, imm6); - const u64 mask = Common::Ones(esize) << shift_amount; + const u64 mask = mcl::bit::ones(esize) << shift_amount; const auto d = ToVector(Q, Vd, D); const auto m = ToVector(Q, Vm, M); @@ -210,11 +212,11 @@ bool TranslatorVisitor::asimd_VSLI(bool D, size_t imm6, size_t Vd, bool L, bool } bool TranslatorVisitor::asimd_VQSHL(bool U, bool D, size_t imm6, size_t Vd, bool op, bool L, bool Q, bool M, size_t Vm) { - if (!L && Common::Bits<3, 5>(imm6) == 0) { + if (!L && mcl::bit::get_bits<3, 5>(imm6) == 0) { return DecodeError(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -248,11 +250,11 @@ bool TranslatorVisitor::asimd_VQSHL(bool U, bool D, size_t imm6, size_t Vd, bool } bool TranslatorVisitor::asimd_VSHL(bool D, size_t imm6, size_t Vd, bool L, bool Q, bool M, size_t Vm) { - if (!L && Common::Bits<3, 5>(imm6) == 0) { + if (!L && mcl::bit::get_bits<3, 5>(imm6) == 0) { return DecodeError(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } @@ -298,11 +300,11 @@ bool TranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bo } bool TranslatorVisitor::asimd_VSHLL(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) { - if (Common::Bits<3, 5>(imm6) == 0) { + if (mcl::bit::get_bits<3, 5>(imm6) == 0) { return DecodeError(); } - if (Common::Bit<0>(Vd)) { + if (mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } @@ -320,15 +322,15 @@ bool TranslatorVisitor::asimd_VSHLL(bool U, bool D, size_t imm6, size_t Vd, bool } bool TranslatorVisitor::asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, bool to_fixed, bool Q, bool M, size_t Vm) { - if (Common::Bits<3, 5>(imm6) == 0) { + if (mcl::bit::get_bits<3, 5>(imm6) == 0) { return DecodeError(); } - if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { + if (Q && (mcl::bit::get_bit<0>(Vd) || mcl::bit::get_bit<0>(Vm))) { return UndefinedInstruction(); } - if (!Common::Bit<5>(imm6)) { + if (!mcl::bit::get_bit<5>(imm6)) { return UndefinedInstruction(); } diff --git a/src/dynarmic/frontend/A32/translate/impl/load_store.cpp b/src/dynarmic/frontend/A32/translate/impl/load_store.cpp index 77df6a4d..7ef8b7e8 100644 --- a/src/dynarmic/frontend/A32/translate/impl/load_store.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/load_store.cpp @@ -3,6 +3,9 @@ * SPDX-License-Identifier: 0BSD */ +#include +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -771,15 +774,15 @@ bool TranslatorVisitor::arm_STRH_reg(Cond cond, bool P, bool U, bool W, Reg n, R static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) { auto address = start_address; for (size_t i = 0; i <= 14; i++) { - if (Common::Bit(i, list)) { + if (mcl::bit::get_bit(i, list)) { ir.SetRegister(static_cast(i), ir.ReadMemory32(address, IR::AccType::ATOMIC)); address = ir.Add(address, ir.Imm32(4)); } } - if (W && !Common::Bit(RegNumber(n), list)) { + if (W && !mcl::bit::get_bit(RegNumber(n), list)) { ir.SetRegister(n, writeback_address); } - if (Common::Bit<15>(list)) { + if (mcl::bit::get_bit<15>(list)) { ir.LoadWritePC(ir.ReadMemory32(address, IR::AccType::ATOMIC)); if (n == Reg::R13) ir.SetTerm(IR::Term::PopRSBHint{}); @@ -792,10 +795,10 @@ static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 s // LDM {!}, bool TranslatorVisitor::arm_LDM(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), list)) { + if (W && mcl::bit::get_bit(static_cast(n), list)) { return UnpredictableInstruction(); } @@ -804,16 +807,16 @@ bool TranslatorVisitor::arm_LDM(Cond cond, bool W, Reg n, RegList list) { } const auto start_address = ir.GetRegister(n); - const auto writeback_address = ir.Add(start_address, ir.Imm32(u32(Common::BitCount(list) * 4))); + const auto writeback_address = ir.Add(start_address, ir.Imm32(u32(mcl::bit::count_ones(list) * 4))); return LDMHelper(ir, W, n, list, start_address, writeback_address); } // LDMDA {!}, bool TranslatorVisitor::arm_LDMDA(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), list)) { + if (W && mcl::bit::get_bit(static_cast(n), list)) { return UnpredictableInstruction(); } @@ -821,17 +824,17 @@ bool TranslatorVisitor::arm_LDMDA(Cond cond, bool W, Reg n, RegList list) { return true; } - const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list) - 4))); + const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * mcl::bit::count_ones(list) - 4))); const auto writeback_address = ir.Sub(start_address, ir.Imm32(4)); return LDMHelper(ir, W, n, list, start_address, writeback_address); } // LDMDB {!}, bool TranslatorVisitor::arm_LDMDB(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), list)) { + if (W && mcl::bit::get_bit(static_cast(n), list)) { return UnpredictableInstruction(); } @@ -839,17 +842,17 @@ bool TranslatorVisitor::arm_LDMDB(Cond cond, bool W, Reg n, RegList list) { return true; } - const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list)))); + const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * mcl::bit::count_ones(list)))); const auto writeback_address = start_address; return LDMHelper(ir, W, n, list, start_address, writeback_address); } // LDMIB {!}, bool TranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), list)) { + if (W && mcl::bit::get_bit(static_cast(n), list)) { return UnpredictableInstruction(); } @@ -858,7 +861,7 @@ bool TranslatorVisitor::arm_LDMIB(Cond cond, bool W, Reg n, RegList list) { } const auto start_address = ir.Add(ir.GetRegister(n), ir.Imm32(4)); - const auto writeback_address = ir.Add(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list)))); + const auto writeback_address = ir.Add(ir.GetRegister(n), ir.Imm32(u32(4 * mcl::bit::count_ones(list)))); return LDMHelper(ir, W, n, list, start_address, writeback_address); } @@ -873,7 +876,7 @@ bool TranslatorVisitor::arm_LDM_eret() { static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 start_address, IR::U32 writeback_address) { auto address = start_address; for (size_t i = 0; i <= 14; i++) { - if (Common::Bit(i, list)) { + if (mcl::bit::get_bit(i, list)) { ir.WriteMemory32(address, ir.GetRegister(static_cast(i)), IR::AccType::ATOMIC); address = ir.Add(address, ir.Imm32(4)); } @@ -881,7 +884,7 @@ static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 s if (W) { ir.SetRegister(n, writeback_address); } - if (Common::Bit<15>(list)) { + if (mcl::bit::get_bit<15>(list)) { ir.WriteMemory32(address, ir.Imm32(ir.PC()), IR::AccType::ATOMIC); } return true; @@ -889,7 +892,7 @@ static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, RegList list, IR::U32 s // STM {!}, bool TranslatorVisitor::arm_STM(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } @@ -898,13 +901,13 @@ bool TranslatorVisitor::arm_STM(Cond cond, bool W, Reg n, RegList list) { } const auto start_address = ir.GetRegister(n); - const auto writeback_address = ir.Add(start_address, ir.Imm32(u32(Common::BitCount(list) * 4))); + const auto writeback_address = ir.Add(start_address, ir.Imm32(u32(mcl::bit::count_ones(list) * 4))); return STMHelper(ir, W, n, list, start_address, writeback_address); } // STMDA {!}, bool TranslatorVisitor::arm_STMDA(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } @@ -912,14 +915,14 @@ bool TranslatorVisitor::arm_STMDA(Cond cond, bool W, Reg n, RegList list) { return true; } - const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list) - 4))); + const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * mcl::bit::count_ones(list) - 4))); const auto writeback_address = ir.Sub(start_address, ir.Imm32(4)); return STMHelper(ir, W, n, list, start_address, writeback_address); } // STMDB {!}, bool TranslatorVisitor::arm_STMDB(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } @@ -927,14 +930,14 @@ bool TranslatorVisitor::arm_STMDB(Cond cond, bool W, Reg n, RegList list) { return true; } - const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list)))); + const auto start_address = ir.Sub(ir.GetRegister(n), ir.Imm32(u32(4 * mcl::bit::count_ones(list)))); const auto writeback_address = start_address; return STMHelper(ir, W, n, list, start_address, writeback_address); } // STMIB {!}, bool TranslatorVisitor::arm_STMIB(Cond cond, bool W, Reg n, RegList list) { - if (n == Reg::PC || Common::BitCount(list) < 1) { + if (n == Reg::PC || mcl::bit::count_ones(list) < 1) { return UnpredictableInstruction(); } @@ -943,7 +946,7 @@ bool TranslatorVisitor::arm_STMIB(Cond cond, bool W, Reg n, RegList list) { } const auto start_address = ir.Add(ir.GetRegister(n), ir.Imm32(4)); - const auto writeback_address = ir.Add(ir.GetRegister(n), ir.Imm32(u32(4 * Common::BitCount(list)))); + const auto writeback_address = ir.Add(ir.GetRegister(n), ir.Imm32(u32(4 * mcl::bit::count_ones(list)))); return STMHelper(ir, W, n, list, start_address, writeback_address); } diff --git a/src/dynarmic/frontend/A32/translate/impl/misc.cpp b/src/dynarmic/frontend/A32/translate/impl/misc.cpp index 8adab9ca..ef54b668 100644 --- a/src/dynarmic/frontend/A32/translate/impl/misc.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/misc.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -23,7 +24,7 @@ bool TranslatorVisitor::arm_BFC(Cond cond, Imm<5> msb, Reg d, Imm<5> lsb) { const u32 lsb_value = lsb.ZeroExtend(); const u32 msb_value = msb.ZeroExtend(); - const u32 mask = ~(Common::Ones(msb_value - lsb_value + 1) << lsb_value); + const u32 mask = ~(mcl::bit::ones(msb_value - lsb_value + 1) << lsb_value); const IR::U32 operand = ir.GetRegister(d); const IR::U32 result = ir.And(operand, ir.Imm32(mask)); @@ -46,7 +47,7 @@ bool TranslatorVisitor::arm_BFI(Cond cond, Imm<5> msb, Reg d, Imm<5> lsb, Reg n) const u32 lsb_value = lsb.ZeroExtend(); const u32 msb_value = msb.ZeroExtend(); - const u32 inclusion_mask = Common::Ones(msb_value - lsb_value + 1) << lsb_value; + const u32 inclusion_mask = mcl::bit::ones(msb_value - lsb_value + 1) << lsb_value; const u32 exclusion_mask = ~inclusion_mask; const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask)); const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(u8(lsb_value))), ir.Imm32(inclusion_mask)); @@ -112,7 +113,7 @@ bool TranslatorVisitor::arm_SBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, R const u32 lsb_value = lsb.ZeroExtend(); const u32 widthm1_value = widthm1.ZeroExtend(); const u32 msb = lsb_value + widthm1_value; - if (msb >= Common::BitSize()) { + if (msb >= mcl::bitsizeof) { return UnpredictableInstruction(); } @@ -120,7 +121,7 @@ bool TranslatorVisitor::arm_SBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, R return true; } - constexpr size_t max_width = Common::BitSize(); + constexpr size_t max_width = mcl::bitsizeof; const u32 width = widthm1_value + 1; const u8 left_shift_amount = static_cast(max_width - width - lsb_value); const u8 right_shift_amount = static_cast(max_width - width); @@ -159,7 +160,7 @@ bool TranslatorVisitor::arm_UBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, R const u32 lsb_value = lsb.ZeroExtend(); const u32 widthm1_value = widthm1.ZeroExtend(); const u32 msb = lsb_value + widthm1_value; - if (msb >= Common::BitSize()) { + if (msb >= mcl::bitsizeof) { return UnpredictableInstruction(); } @@ -168,7 +169,7 @@ bool TranslatorVisitor::arm_UBFX(Cond cond, Imm<5> widthm1, Reg d, Imm<5> lsb, R } const IR::U32 operand = ir.GetRegister(n); - const IR::U32 mask = ir.Imm32(Common::Ones(widthm1_value + 1)); + const IR::U32 mask = ir.Imm32(mcl::bit::ones(widthm1_value + 1)); const IR::U32 result = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(u8(lsb_value))), mask); ir.SetRegister(d, result); diff --git a/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp b/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp index d2df86e8..60110df8 100644 --- a/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -29,16 +30,16 @@ bool TranslatorVisitor::arm_MRS(Cond cond, Reg d) { } // MSR , # -bool TranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm<8> imm8) { +bool TranslatorVisitor::arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8) { ASSERT_MSG(mask != 0, "Decode error"); if (!ArmConditionPassed(cond)) { return true; } - const bool write_nzcvq = Common::Bit<3>(mask); - const bool write_g = Common::Bit<2>(mask); - const bool write_e = Common::Bit<1>(mask); + const bool write_nzcvq = mcl::bit::get_bit<3>(mask); + const bool write_g = mcl::bit::get_bit<2>(mask); + const bool write_e = mcl::bit::get_bit<1>(mask); const u32 imm32 = ArmExpandImm(rotate, imm8); if (write_nzcvq) { @@ -61,7 +62,7 @@ bool TranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm<8> imm8 } // MSR , -bool TranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) { +bool TranslatorVisitor::arm_MSR_reg(Cond cond, unsigned mask, Reg n) { if (mask == 0) { return UnpredictableInstruction(); } @@ -74,9 +75,9 @@ bool TranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) { return true; } - const bool write_nzcvq = Common::Bit<3>(mask); - const bool write_g = Common::Bit<2>(mask); - const bool write_e = Common::Bit<1>(mask); + const bool write_nzcvq = mcl::bit::get_bit<3>(mask); + const bool write_g = mcl::bit::get_bit<2>(mask); + const bool write_e = mcl::bit::get_bit<1>(mask); const auto value = ir.GetRegister(n); if (!write_e) { diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp index dbaf5f08..0c531e9f 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" #include "dynarmic/interface/A32/config.h" @@ -705,7 +707,7 @@ bool TranslatorVisitor::thumb16_NOP() { // IT{{{}}} bool TranslatorVisitor::thumb16_IT(Imm<8> imm8) { ASSERT_MSG((imm8.Bits<0, 3>() != 0b0000), "Decode Error"); - if (imm8.Bits<4, 7>() == 0b1111 || (imm8.Bits<4, 7>() == 0b1110 && Common::BitCount(imm8.Bits<0, 3>()) != 1)) { + if (imm8.Bits<4, 7>() == 0b1111 || (imm8.Bits<4, 7>() == 0b1110 && mcl::bit::count_ones(imm8.Bits<0, 3>()) != 1)) { return UnpredictableInstruction(); } if (ir.current_location.IT().IsInITBlock()) { @@ -755,15 +757,15 @@ bool TranslatorVisitor::thumb16_PUSH(bool M, RegList reg_list) { if (M) { reg_list |= 1 << 14; } - if (Common::BitCount(reg_list) < 1) { + if (mcl::bit::count_ones(reg_list) < 1) { return UnpredictableInstruction(); } - const u32 num_bytes_to_push = static_cast(4 * Common::BitCount(reg_list)); + const u32 num_bytes_to_push = static_cast(4 * mcl::bit::count_ones(reg_list)); const auto final_address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(num_bytes_to_push)); auto address = final_address; for (size_t i = 0; i < 16; i++) { - if (Common::Bit(i, reg_list)) { + if (mcl::bit::get_bit(i, reg_list)) { // TODO: Deal with alignment const auto Ri = ir.GetRegister(static_cast(i)); ir.WriteMemory32(address, Ri, IR::AccType::ATOMIC); @@ -781,13 +783,13 @@ bool TranslatorVisitor::thumb16_POP(bool P, RegList reg_list) { if (P) { reg_list |= 1 << 15; } - if (Common::BitCount(reg_list) < 1) { + if (mcl::bit::count_ones(reg_list) < 1) { return UnpredictableInstruction(); } auto address = ir.GetRegister(Reg::SP); for (size_t i = 0; i < 15; i++) { - if (Common::Bit(i, reg_list)) { + if (mcl::bit::get_bit(i, reg_list)) { // TODO: Deal with alignment const auto data = ir.ReadMemory32(address, IR::AccType::ATOMIC); ir.SetRegister(static_cast(i), data); @@ -795,7 +797,7 @@ bool TranslatorVisitor::thumb16_POP(bool P, RegList reg_list) { } } - if (Common::Bit<15>(reg_list)) { + if (mcl::bit::get_bit<15>(reg_list)) { // TODO(optimization): Possible location for an RSB pop. const auto data = ir.ReadMemory32(address, IR::AccType::ATOMIC); ir.UpdateUpperLocationDescriptor(); @@ -868,16 +870,16 @@ bool TranslatorVisitor::thumb16_BKPT(Imm<8> /*imm8*/) { // STM !, bool TranslatorVisitor::thumb16_STMIA(Reg n, RegList reg_list) { - if (Common::BitCount(reg_list) == 0) { + if (mcl::bit::count_ones(reg_list) == 0) { return UnpredictableInstruction(); } - if (Common::Bit(static_cast(n), reg_list) && n != static_cast(Common::LowestSetBit(reg_list))) { + if (mcl::bit::get_bit(static_cast(n), reg_list) && n != static_cast(mcl::bit::lowest_set_bit(reg_list))) { return UnpredictableInstruction(); } auto address = ir.GetRegister(n); for (size_t i = 0; i < 8; i++) { - if (Common::Bit(i, reg_list)) { + if (mcl::bit::get_bit(i, reg_list)) { const auto Ri = ir.GetRegister(static_cast(i)); ir.WriteMemory32(address, Ri, IR::AccType::ATOMIC); address = ir.Add(address, ir.Imm32(4)); @@ -890,15 +892,15 @@ bool TranslatorVisitor::thumb16_STMIA(Reg n, RegList reg_list) { // LDM !, bool TranslatorVisitor::thumb16_LDMIA(Reg n, RegList reg_list) { - if (Common::BitCount(reg_list) == 0) { + if (mcl::bit::count_ones(reg_list) == 0) { return UnpredictableInstruction(); } - const bool write_back = !Common::Bit(static_cast(n), reg_list); + const bool write_back = !mcl::bit::get_bit(static_cast(n), reg_list); auto address = ir.GetRegister(n); for (size_t i = 0; i < 8; i++) { - if (Common::Bit(i, reg_list)) { + if (mcl::bit::get_bit(i, reg_list)) { const auto data = ir.ReadMemory32(address, IR::AccType::ATOMIC); ir.SetRegister(static_cast(i), data); address = ir.Add(address, ir.Imm32(4)); diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp index 358b7d7b..1a6767db 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp @@ -3,8 +3,9 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -101,7 +102,7 @@ bool TranslatorVisitor::thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) return UnpredictableInstruction(); } - const u32 mask = ~(Common::Ones(msbit - lsbit + 1) << lsbit); + const u32 mask = ~(mcl::bit::ones(msbit - lsbit + 1) << lsbit); const auto reg_d = ir.GetRegister(d); const auto result = ir.And(reg_d, ir.Imm32(mask)); @@ -121,7 +122,7 @@ bool TranslatorVisitor::thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm< return UnpredictableInstruction(); } - const u32 inclusion_mask = Common::Ones(msbit - lsbit + 1) << lsbit; + const u32 inclusion_mask = mcl::bit::ones(msbit - lsbit + 1) << lsbit; const u32 exclusion_mask = ~inclusion_mask; const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask)); const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(u8(lsbit))), ir.Imm32(inclusion_mask)); @@ -163,11 +164,11 @@ bool TranslatorVisitor::thumb32_SBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm const u32 lsbit = concatenate(imm3, imm2).ZeroExtend(); const u32 widthm1_value = widthm1.ZeroExtend(); const u32 msb = lsbit + widthm1_value; - if (msb >= Common::BitSize()) { + if (msb >= mcl::bitsizeof) { return UnpredictableInstruction(); } - constexpr size_t max_width = Common::BitSize(); + constexpr size_t max_width = mcl::bitsizeof; const auto width = widthm1_value + 1; const auto left_shift_amount = static_cast(max_width - width - lsbit); const auto right_shift_amount = static_cast(max_width - width); @@ -208,12 +209,12 @@ bool TranslatorVisitor::thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm const u32 lsbit = concatenate(imm3, imm2).ZeroExtend(); const u32 widthm1_value = widthm1.ZeroExtend(); const u32 msb = lsbit + widthm1_value; - if (msb >= Common::BitSize()) { + if (msb >= mcl::bitsizeof) { return UnpredictableInstruction(); } const auto operand = ir.GetRegister(n); - const auto mask = ir.Imm32(Common::Ones(widthm1_value + 1)); + const auto mask = ir.Imm32(mcl::bit::ones(widthm1_value + 1)); const auto result = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(u8(lsbit))), mask); ir.SetRegister(d, result); diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp index 374cc906..17d4285c 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_dual.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { diff --git a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp index c4ff0766..2bc782b9 100644 --- a/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/thumb32_load_store_multiple.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" namespace Dynarmic::A32 { @@ -14,15 +15,15 @@ static bool ITBlockCheck(const A32::IREmitter& ir) { static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32& start_address, const IR::U32& writeback_address) { auto address = start_address; for (size_t i = 0; i <= 14; i++) { - if (Common::Bit(i, list)) { + if (mcl::bit::get_bit(i, list)) { ir.SetRegister(static_cast(i), ir.ReadMemory32(address, IR::AccType::ATOMIC)); address = ir.Add(address, ir.Imm32(4)); } } - if (W && !Common::Bit(RegNumber(n), list)) { + if (W && !mcl::bit::get_bit(RegNumber(n), list)) { ir.SetRegister(n, writeback_address); } - if (Common::Bit<15>(list)) { + if (mcl::bit::get_bit<15>(list)) { ir.UpdateUpperLocationDescriptor(); ir.LoadWritePC(ir.ReadMemory32(address, IR::AccType::ATOMIC)); if (n == Reg::R13) { @@ -38,7 +39,7 @@ static bool LDMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32 static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32& start_address, const IR::U32& writeback_address) { auto address = start_address; for (size_t i = 0; i <= 14; i++) { - if (Common::Bit(i, list)) { + if (mcl::bit::get_bit(i, list)) { ir.WriteMemory32(address, ir.GetRegister(static_cast(i)), IR::AccType::ATOMIC); address = ir.Add(address, ir.Imm32(4)); } @@ -51,7 +52,7 @@ static bool STMHelper(A32::IREmitter& ir, bool W, Reg n, u32 list, const IR::U32 bool TranslatorVisitor::thumb32_LDMDB(bool W, Reg n, Imm<16> reg_list) { const auto regs_imm = reg_list.ZeroExtend(); - const auto num_regs = static_cast(Common::BitCount(regs_imm)); + const auto num_regs = static_cast(mcl::bit::count_ones(regs_imm)); if (n == Reg::PC || num_regs < 2) { return UnpredictableInstruction(); @@ -59,7 +60,7 @@ bool TranslatorVisitor::thumb32_LDMDB(bool W, Reg n, Imm<16> reg_list) { if (reg_list.Bit<15>() && reg_list.Bit<14>()) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), regs_imm)) { + if (W && mcl::bit::get_bit(static_cast(n), regs_imm)) { return UnpredictableInstruction(); } if (reg_list.Bit<13>()) { @@ -76,7 +77,7 @@ bool TranslatorVisitor::thumb32_LDMDB(bool W, Reg n, Imm<16> reg_list) { bool TranslatorVisitor::thumb32_LDMIA(bool W, Reg n, Imm<16> reg_list) { const auto regs_imm = reg_list.ZeroExtend(); - const auto num_regs = static_cast(Common::BitCount(regs_imm)); + const auto num_regs = static_cast(mcl::bit::count_ones(regs_imm)); if (n == Reg::PC || num_regs < 2) { return UnpredictableInstruction(); @@ -84,7 +85,7 @@ bool TranslatorVisitor::thumb32_LDMIA(bool W, Reg n, Imm<16> reg_list) { if (reg_list.Bit<15>() && reg_list.Bit<14>()) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), regs_imm)) { + if (W && mcl::bit::get_bit(static_cast(n), regs_imm)) { return UnpredictableInstruction(); } if (reg_list.Bit<13>()) { @@ -109,12 +110,12 @@ bool TranslatorVisitor::thumb32_PUSH(Imm<15> reg_list) { bool TranslatorVisitor::thumb32_STMIA(bool W, Reg n, Imm<15> reg_list) { const auto regs_imm = reg_list.ZeroExtend(); - const auto num_regs = static_cast(Common::BitCount(regs_imm)); + const auto num_regs = static_cast(mcl::bit::count_ones(regs_imm)); if (n == Reg::PC || num_regs < 2) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), regs_imm)) { + if (W && mcl::bit::get_bit(static_cast(n), regs_imm)) { return UnpredictableInstruction(); } if (reg_list.Bit<13>()) { @@ -128,12 +129,12 @@ bool TranslatorVisitor::thumb32_STMIA(bool W, Reg n, Imm<15> reg_list) { bool TranslatorVisitor::thumb32_STMDB(bool W, Reg n, Imm<15> reg_list) { const auto regs_imm = reg_list.ZeroExtend(); - const auto num_regs = static_cast(Common::BitCount(regs_imm)); + const auto num_regs = static_cast(mcl::bit::count_ones(regs_imm)); if (n == Reg::PC || num_regs < 2) { return UnpredictableInstruction(); } - if (W && Common::Bit(static_cast(n), regs_imm)) { + if (W && mcl::bit::get_bit(static_cast(n), regs_imm)) { return UnpredictableInstruction(); } if (reg_list.Bit<13>()) { diff --git a/src/dynarmic/frontend/A32/translate/impl/vfp.cpp b/src/dynarmic/frontend/A32/translate/impl/vfp.cpp index f68c8f38..2e7734ca 100644 --- a/src/dynarmic/frontend/A32/translate/impl/vfp.cpp +++ b/src/dynarmic/frontend/A32/translate/impl/vfp.cpp @@ -661,7 +661,7 @@ bool TranslatorVisitor::vfp_VDUP(Cond cond, Imm<1> B, bool Q, size_t Vd, Reg t, return true; } - if (Q && Common::Bit<0>(Vd)) { + if (Q && mcl::bit::get_bit<0>(Vd)) { return UndefinedInstruction(); } if (t == Reg::R15) { diff --git a/src/dynarmic/frontend/A32/translate/translate_arm.cpp b/src/dynarmic/frontend/A32/translate/translate_arm.cpp index 384fa677..95c704da 100644 --- a/src/dynarmic/frontend/A32/translate/translate_arm.cpp +++ b/src/dynarmic/frontend/A32/translate/translate_arm.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/assert.h" +#include + #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/frontend/A32/decoder/arm.h" diff --git a/src/dynarmic/frontend/A32/translate/translate_callbacks.h b/src/dynarmic/frontend/A32/translate/translate_callbacks.h index eeffd9d4..8e0bba3a 100644 --- a/src/dynarmic/frontend/A32/translate/translate_callbacks.h +++ b/src/dynarmic/frontend/A32/translate/translate_callbacks.h @@ -4,7 +4,7 @@ */ #pragma once -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::A32 { diff --git a/src/dynarmic/frontend/A32/translate/translate_thumb.cpp b/src/dynarmic/frontend/A32/translate/translate_thumb.cpp index 08bbbadc..9716f11f 100644 --- a/src/dynarmic/frontend/A32/translate/translate_thumb.cpp +++ b/src/dynarmic/frontend/A32/translate/translate_thumb.cpp @@ -5,8 +5,10 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include +#include + #include "dynarmic/frontend/A32/a32_ir_emitter.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/decoder/asimd.h" @@ -69,7 +71,7 @@ std::tuple ReadThumbInstruction(u32 arm_pc, TranslateCallbac // Convert from thumb ASIMD format to ARM ASIMD format. u32 ConvertASIMDInstruction(u32 thumb_instruction) { if ((thumb_instruction & 0xEF000000) == 0xEF000000) { - const bool U = Common::Bit<28>(thumb_instruction); + const bool U = mcl::bit::get_bit<28>(thumb_instruction); return 0xF2000000 | (U << 24) | (thumb_instruction & 0x00FFFFFF); } @@ -167,7 +169,7 @@ bool TranslateSingleThumbInstruction(IR::Block& block, LocationDescriptor descri should_continue = visitor.thumb16_UDF(); } } else { - thumb_instruction = Common::SwapHalves32(thumb_instruction); + thumb_instruction = mcl::bit::swap_halves_32(thumb_instruction); if (MaybeVFPOrASIMDInstruction(thumb_instruction)) { if (const auto vfp_decoder = DecodeVFP(thumb_instruction)) { should_continue = vfp_decoder->get().call(visitor, thumb_instruction); diff --git a/src/dynarmic/frontend/A64/a64_ir_emitter.cpp b/src/dynarmic/frontend/A64/a64_ir_emitter.cpp index e4ea1f5e..d0c038b4 100644 --- a/src/dynarmic/frontend/A64/a64_ir_emitter.cpp +++ b/src/dynarmic/frontend/A64/a64_ir_emitter.cpp @@ -5,7 +5,8 @@ #include "dynarmic/frontend/A64/a64_ir_emitter.h" -#include "dynarmic/common/assert.h" +#include + #include "dynarmic/ir/opcodes.h" namespace Dynarmic::A64 { diff --git a/src/dynarmic/frontend/A64/a64_ir_emitter.h b/src/dynarmic/frontend/A64/a64_ir_emitter.h index 56ad7673..7bb71bea 100644 --- a/src/dynarmic/frontend/A64/a64_ir_emitter.h +++ b/src/dynarmic/frontend/A64/a64_ir_emitter.h @@ -7,7 +7,8 @@ #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/interface/A64/config.h" diff --git a/src/dynarmic/frontend/A64/a64_location_descriptor.h b/src/dynarmic/frontend/A64/a64_location_descriptor.h index 322cea3b..3301616f 100644 --- a/src/dynarmic/frontend/A64/a64_location_descriptor.h +++ b/src/dynarmic/frontend/A64/a64_location_descriptor.h @@ -9,8 +9,9 @@ #include #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/ir/location_descriptor.h" @@ -24,7 +25,7 @@ namespace Dynarmic::A64 { class LocationDescriptor { public: static constexpr size_t pc_bit_count = 56; - static constexpr u64 pc_mask = Common::Ones(pc_bit_count); + static constexpr u64 pc_mask = mcl::bit::ones(pc_bit_count); static constexpr u32 fpcr_mask = 0x07C8'0000; static constexpr size_t fpcr_shift = 37; static constexpr size_t single_stepping_bit = 57; @@ -36,9 +37,9 @@ public: explicit LocationDescriptor(const IR::LocationDescriptor& o) : pc(o.Value() & pc_mask) , fpcr((o.Value() >> fpcr_shift) & fpcr_mask) - , single_stepping(Common::Bit(o.Value())) {} + , single_stepping(mcl::bit::get_bit(o.Value())) {} - u64 PC() const { return Common::SignExtend(pc); } + u64 PC() const { return mcl::bit::sign_extend(pc); } FP::FPCR FPCR() const { return fpcr; } bool SingleStepping() const { return single_stepping; } diff --git a/src/dynarmic/frontend/A64/a64_types.h b/src/dynarmic/frontend/A64/a64_types.h index 6e12754c..3bcb84aa 100644 --- a/src/dynarmic/frontend/A64/a64_types.h +++ b/src/dynarmic/frontend/A64/a64_types.h @@ -8,8 +8,9 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/ir/cond.h" namespace Dynarmic::A64 { diff --git a/src/dynarmic/frontend/A64/decoder/a64.h b/src/dynarmic/frontend/A64/decoder/a64.h index 7da60e30..d6f447e5 100644 --- a/src/dynarmic/frontend/A64/decoder/a64.h +++ b/src/dynarmic/frontend/A64/decoder/a64.h @@ -12,8 +12,9 @@ #include #include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/frontend/decoder/decoder_detail.h" #include "dynarmic/frontend/decoder/matcher.h" @@ -41,7 +42,7 @@ DecodeTable GetDecodeTable() { std::stable_sort(list.begin(), list.end(), [](const auto& matcher1, const auto& matcher2) { // If a matcher has more bits in its mask it is more specific, so it should come first. - return Common::BitCount(matcher1.GetMask()) > Common::BitCount(matcher2.GetMask()); + return mcl::bit::count_ones(matcher1.GetMask()) > mcl::bit::count_ones(matcher2.GetMask()); }); // Exceptions to the above rule of thumb. diff --git a/src/dynarmic/frontend/A64/translate/a64_translate.h b/src/dynarmic/frontend/A64/translate/a64_translate.h index 9ab6d264..d61f5e86 100644 --- a/src/dynarmic/frontend/A64/translate/a64_translate.h +++ b/src/dynarmic/frontend/A64/translate/a64_translate.h @@ -6,7 +6,7 @@ #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic { diff --git a/src/dynarmic/frontend/A64/translate/impl/impl.cpp b/src/dynarmic/frontend/A64/translate/impl/impl.cpp index 24607ef7..d0fd9386 100644 --- a/src/dynarmic/frontend/A64/translate/impl/impl.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/impl.cpp @@ -5,7 +5,10 @@ #include "dynarmic/frontend/A64/translate/impl/impl.h" -#include "dynarmic/common/bit_util.h" +#include +#include +#include + #include "dynarmic/ir/terminal.h" namespace Dynarmic::A64 { @@ -39,12 +42,12 @@ bool TranslatorVisitor::RaiseException(Exception exception) { } std::optional TranslatorVisitor::DecodeBitMasks(bool immN, Imm<6> imms, Imm<6> immr, bool immediate) { - const int len = Common::HighestSetBit((immN ? 1 << 6 : 0) | (imms.ZeroExtend() ^ 0b111111)); + const int len = mcl::bit::highest_set_bit((immN ? 1 << 6 : 0) | (imms.ZeroExtend() ^ 0b111111)); if (len < 1) { return std::nullopt; } - const size_t levels = Common::Ones(len); + const size_t levels = mcl::bit::ones(len); if (immediate && (imms.ZeroExtend() & levels) == levels) { return std::nullopt; } @@ -54,10 +57,10 @@ std::optional TranslatorVisitor::DecodeBitMasks(boo const u64 d = u64(S - R) & levels; const size_t esize = size_t{1} << len; - const u64 welem = Common::Ones(S + 1); - const u64 telem = Common::Ones(d + 1); - const u64 wmask = Common::RotateRight(Common::Replicate(welem, esize), R); - const u64 tmask = Common::Replicate(telem, esize); + const u64 welem = mcl::bit::ones(S + 1); + const u64 telem = mcl::bit::ones(d + 1); + const u64 wmask = mcl::bit::rotate_right(mcl::bit::replicate_element(esize, welem), R); + const u64 tmask = mcl::bit::replicate_element(esize, telem); return BitMasks{wmask, tmask}; } diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp index 38697bb5..b33bc8f5 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_copy.cpp @@ -3,13 +3,14 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { bool TranslatorVisitor::DUP_elt_1(Imm<5> imm5, Vec Vn, Vec Vd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size > 3) { return ReservedValue(); } @@ -26,7 +27,7 @@ bool TranslatorVisitor::DUP_elt_1(Imm<5> imm5, Vec Vn, Vec Vd) { } bool TranslatorVisitor::DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size > 3) { return ReservedValue(); } @@ -47,7 +48,7 @@ bool TranslatorVisitor::DUP_elt_2(bool Q, Imm<5> imm5, Vec Vn, Vec Vd) { } bool TranslatorVisitor::DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size > 3) { return ReservedValue(); } @@ -69,7 +70,7 @@ bool TranslatorVisitor::DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) { } bool TranslatorVisitor::SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size == 2 && !Q) { return UnallocatedEncoding(); } @@ -92,7 +93,7 @@ bool TranslatorVisitor::SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) { } bool TranslatorVisitor::UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size < 3 && Q) { return UnallocatedEncoding(); } @@ -119,7 +120,7 @@ bool TranslatorVisitor::UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) { } bool TranslatorVisitor::INS_gen(Imm<5> imm5, Reg Rn, Vec Vd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size > 3) { return ReservedValue(); } @@ -136,7 +137,7 @@ bool TranslatorVisitor::INS_gen(Imm<5> imm5, Reg Rn, Vec Vd) { } bool TranslatorVisitor::INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd) { - const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + const size_t size = mcl::bit::lowest_set_bit(imm5.ZeroExtend()); if (size > 3) { return ReservedValue(); } diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp index ed45bf59..db8e8363 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_modified_immediate.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { @@ -119,7 +120,7 @@ bool TranslatorVisitor::FMOV_3(bool Q, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, I imm16 |= imm8.Bits<0, 5, u16>() << 6; return imm16; }(); - const u64 imm64 = Common::Replicate(imm16, 16); + const u64 imm64 = mcl::bit::replicate_element(imm16); const IR::U128 imm = datasize == 64 ? ir.ZeroExtendToQuad(ir.Imm64(imm64)) : ir.VectorBroadcast(64, ir.Imm64(imm64)); V(128, Vd, imm); diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp index af1ef9fe..042213de 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp @@ -3,6 +3,8 @@ * SPDX-License-Identifier: 0BSD */ +#include + #include "dynarmic/common/fp/rounding_mode.h" #include "dynarmic/frontend/A64/translate/impl/impl.h" @@ -40,7 +42,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, return v.ReservedValue(); } - const size_t esize = 8U << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8U << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t shift_amount = concatenate(immh, immb).ZeroExtend() - esize; const IR::U128 operand = v.ir.ZeroExtendToQuad(v.V_scalar(esize, Vn)); @@ -139,10 +141,10 @@ bool ShiftAndInsert(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec const u64 mask = [&] { if (direction == ShiftDirection::Right) { - return shift_amount == esize ? 0 : Common::Ones(esize) >> shift_amount; + return shift_amount == esize ? 0 : mcl::bit::ones(esize) >> shift_amount; } - return Common::Ones(esize) << shift_amount; + return mcl::bit::ones(esize) << shift_amount; }(); const IR::U64 operand1 = v.V_scalar(esize, Vn); @@ -170,7 +172,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, return v.ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t source_esize = 2 * esize; const u8 shift_amount = static_cast(source_esize - concatenate(immh, immb).ZeroExtend()); diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp index 76ef26ad..af1adbe3 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_scalar_three_same.cpp @@ -5,7 +5,8 @@ #include -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index f39ccd0f..ee36423f 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/bit_util.h" +#include + #include "dynarmic/common/fp/rounding_mode.h" #include "dynarmic/frontend/A64/translate/impl/impl.h" @@ -56,7 +57,7 @@ bool ShiftRight(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, return v.ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = Q ? 128 : 64; const u8 shift_amount = static_cast(2 * esize) - concatenate(immh, immb).ZeroExtend(); @@ -93,7 +94,7 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, return v.ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t source_esize = 2 * esize; const size_t part = Q ? 1 : 0; @@ -142,7 +143,7 @@ bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec V return v.ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = 64; const size_t part = Q ? 1 : 0; @@ -166,7 +167,7 @@ bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, return v.ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = Q ? 128 : 64; const size_t shift = concatenate(immh, immb).ZeroExtend() - esize; @@ -201,7 +202,7 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn return v.ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = Q ? 128 : 64; const u8 fbits = static_cast(esize * 2) - concatenate(immh, immb).ZeroExtend(); @@ -250,7 +251,7 @@ bool TranslatorVisitor::SHL_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) if (immh.Bit<3>() && !Q) { return ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = Q ? 128 : 64; const u8 shift_amount = concatenate(immh, immb).ZeroExtend() - static_cast(esize); @@ -339,11 +340,11 @@ bool TranslatorVisitor::SRI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) return ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = Q ? 128 : 64; const u8 shift_amount = static_cast((esize * 2) - concatenate(immh, immb).ZeroExtend()); - const u64 mask = shift_amount == esize ? 0 : Common::Ones(esize) >> shift_amount; + const u64 mask = shift_amount == esize ? 0 : mcl::bit::ones(esize) >> shift_amount; const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(datasize, Vd); @@ -365,11 +366,11 @@ bool TranslatorVisitor::SLI_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) return ReservedValue(); } - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t esize = 8 << mcl::bit::highest_set_bit(immh.ZeroExtend()); const size_t datasize = Q ? 128 : 64; const u8 shift_amount = concatenate(immh, immb).ZeroExtend() - static_cast(esize); - const u64 mask = Common::Ones(esize) << shift_amount; + const u64 mask = mcl::bit::ones(esize) << shift_amount; const IR::U128 operand1 = V(datasize, Vn); const IR::U128 operand2 = V(datasize, Vd); diff --git a/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp b/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp index 3d46c07d..8b76e290 100644 --- a/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp +++ b/src/dynarmic/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp @@ -5,7 +5,8 @@ #include -#include "dynarmic/common/assert.h" +#include + #include "dynarmic/frontend/A64/translate/impl/impl.h" namespace Dynarmic::A64 { diff --git a/src/dynarmic/frontend/decoder/decoder_detail.h b/src/dynarmic/frontend/decoder/decoder_detail.h index d309e6b0..55d745c7 100644 --- a/src/dynarmic/frontend/decoder/decoder_detail.h +++ b/src/dynarmic/frontend/decoder/decoder_detail.h @@ -9,11 +9,10 @@ #include #include +#include +#include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" - namespace Dynarmic::Decoder { namespace detail { @@ -36,7 +35,7 @@ struct detail { using opcode_type = typename MatcherT::opcode_type; using visitor_type = typename MatcherT::visitor_type; - static constexpr size_t opcode_bitsize = Common::BitSize(); + static constexpr size_t opcode_bitsize = mcl::bitsizeof; /** * Generates the mask and the expected value after masking from a given bitstring. diff --git a/src/dynarmic/frontend/decoder/matcher.h b/src/dynarmic/frontend/decoder/matcher.h index 54c2d116..adf9556d 100644 --- a/src/dynarmic/frontend/decoder/matcher.h +++ b/src/dynarmic/frontend/decoder/matcher.h @@ -7,7 +7,7 @@ #include -#include "dynarmic/common/assert.h" +#include namespace Dynarmic::Decoder { diff --git a/src/dynarmic/frontend/imm.cpp b/src/dynarmic/frontend/imm.cpp index 72d1e8fe..c802864d 100644 --- a/src/dynarmic/frontend/imm.cpp +++ b/src/dynarmic/frontend/imm.cpp @@ -5,45 +5,45 @@ #include "dynarmic/frontend/imm.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include namespace Dynarmic { u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) { switch (cmode.Bits<1, 3>()) { case 0b000: - return Common::Replicate(imm8.ZeroExtend(), 32); + return mcl::bit::replicate_element(imm8.ZeroExtend()); case 0b001: - return Common::Replicate(imm8.ZeroExtend() << 8, 32); + return mcl::bit::replicate_element(imm8.ZeroExtend() << 8); case 0b010: - return Common::Replicate(imm8.ZeroExtend() << 16, 32); + return mcl::bit::replicate_element(imm8.ZeroExtend() << 16); case 0b011: - return Common::Replicate(imm8.ZeroExtend() << 24, 32); + return mcl::bit::replicate_element(imm8.ZeroExtend() << 24); case 0b100: - return Common::Replicate(imm8.ZeroExtend(), 16); + return mcl::bit::replicate_element(imm8.ZeroExtend()); case 0b101: - return Common::Replicate(imm8.ZeroExtend() << 8, 16); + return mcl::bit::replicate_element(imm8.ZeroExtend() << 8); case 0b110: if (!cmode.Bit<0>()) { - return Common::Replicate((imm8.ZeroExtend() << 8) | Common::Ones(8), 32); + return mcl::bit::replicate_element((imm8.ZeroExtend() << 8) | mcl::bit::ones(8)); } - return Common::Replicate((imm8.ZeroExtend() << 16) | Common::Ones(16), 32); + return mcl::bit::replicate_element((imm8.ZeroExtend() << 16) | mcl::bit::ones(16)); case 0b111: if (!cmode.Bit<0>() && !op) { - return Common::Replicate(imm8.ZeroExtend(), 8); + return mcl::bit::replicate_element(imm8.ZeroExtend()); } if (!cmode.Bit<0>() && op) { u64 result = 0; - result |= imm8.Bit<0>() ? Common::Ones(8) << (0 * 8) : 0; - result |= imm8.Bit<1>() ? Common::Ones(8) << (1 * 8) : 0; - result |= imm8.Bit<2>() ? Common::Ones(8) << (2 * 8) : 0; - result |= imm8.Bit<3>() ? Common::Ones(8) << (3 * 8) : 0; - result |= imm8.Bit<4>() ? Common::Ones(8) << (4 * 8) : 0; - result |= imm8.Bit<5>() ? Common::Ones(8) << (5 * 8) : 0; - result |= imm8.Bit<6>() ? Common::Ones(8) << (6 * 8) : 0; - result |= imm8.Bit<7>() ? Common::Ones(8) << (7 * 8) : 0; + result |= imm8.Bit<0>() ? mcl::bit::ones(8) << (0 * 8) : 0; + result |= imm8.Bit<1>() ? mcl::bit::ones(8) << (1 * 8) : 0; + result |= imm8.Bit<2>() ? mcl::bit::ones(8) << (2 * 8) : 0; + result |= imm8.Bit<3>() ? mcl::bit::ones(8) << (3 * 8) : 0; + result |= imm8.Bit<4>() ? mcl::bit::ones(8) << (4 * 8) : 0; + result |= imm8.Bit<5>() ? mcl::bit::ones(8) << (5 * 8) : 0; + result |= imm8.Bit<6>() ? mcl::bit::ones(8) << (6 * 8) : 0; + result |= imm8.Bit<7>() ? mcl::bit::ones(8) << (7 * 8) : 0; return result; } if (cmode.Bit<0>() && !op) { @@ -51,7 +51,7 @@ u64 AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) { result |= imm8.Bit<7>() ? 0x80000000 : 0; result |= imm8.Bit<6>() ? 0x3E000000 : 0x40000000; result |= imm8.Bits<0, 5, u64>() << 19; - return Common::Replicate(result, 32); + return mcl::bit::replicate_element(result); } if (cmode.Bit<0>() && op) { u64 result = 0; diff --git a/src/dynarmic/frontend/imm.h b/src/dynarmic/frontend/imm.h index d534d866..7d86abbb 100644 --- a/src/dynarmic/frontend/imm.h +++ b/src/dynarmic/frontend/imm.h @@ -5,9 +5,13 @@ #pragma once -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include + +#include +#include +#include +#include + #include "dynarmic/common/math_util.h" namespace Dynarmic { @@ -23,32 +27,32 @@ public: explicit Imm(u32 value) : value(value) { - ASSERT_MSG((Common::Bits<0, bit_size - 1>(value) == value), "More bits in value than expected"); + ASSERT_MSG((mcl::bit::get_bits<0, bit_size - 1>(value) == value), "More bits in value than expected"); } template T ZeroExtend() const { - static_assert(Common::BitSize() >= bit_size); + static_assert(mcl::bitsizeof >= bit_size); return static_cast(value); } template T SignExtend() const { - static_assert(Common::BitSize() >= bit_size); - return Common::SignExtend(value); + static_assert(mcl::bitsizeof >= bit_size); + return static_cast(mcl::bit::sign_extend>(value)); } template bool Bit() const { static_assert(bit < bit_size); - return Common::Bit(value); + return mcl::bit::get_bit(value); } template T Bits() const { static_assert(begin_bit <= end_bit && end_bit < bit_size); - static_assert(Common::BitSize() >= end_bit - begin_bit + 1); - return static_cast(Common::Bits(value)); + static_assert(mcl::bitsizeof >= end_bit - begin_bit + 1); + return static_cast(mcl::bit::get_bits(value)); } bool operator==(Imm other) const { diff --git a/src/dynarmic/ir/basic_block.cpp b/src/dynarmic/ir/basic_block.cpp index c1f66ef3..da7f837b 100644 --- a/src/dynarmic/ir/basic_block.cpp +++ b/src/dynarmic/ir/basic_block.cpp @@ -12,8 +12,8 @@ #include #include +#include -#include "dynarmic/common/assert.h" #include "dynarmic/common/memory_pool.h" #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/frontend/A64/a64_types.h" diff --git a/src/dynarmic/ir/basic_block.h b/src/dynarmic/ir/basic_block.h index 4f9a7805..18d7fada 100644 --- a/src/dynarmic/ir/basic_block.h +++ b/src/dynarmic/ir/basic_block.h @@ -10,8 +10,9 @@ #include #include -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/intrusive_list.h" +#include +#include + #include "dynarmic/ir/location_descriptor.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/terminal.h" @@ -34,7 +35,7 @@ enum class Opcode; */ class Block final { public: - using InstructionList = Common::IntrusiveList; + using InstructionList = mcl::intrusive_list; using size_type = InstructionList::size_type; using iterator = InstructionList::iterator; using const_iterator = InstructionList::const_iterator; diff --git a/src/dynarmic/ir/ir_emitter.cpp b/src/dynarmic/ir/ir_emitter.cpp index dfb03ae9..f588d3db 100644 --- a/src/dynarmic/ir/ir_emitter.cpp +++ b/src/dynarmic/ir/ir_emitter.cpp @@ -5,8 +5,9 @@ #include "dynarmic/ir/ir_emitter.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/cast_util.h" +#include +#include + #include "dynarmic/ir/opcodes.h" namespace Dynarmic::IR { @@ -2717,19 +2718,19 @@ void IREmitter::Breakpoint() { } void IREmitter::CallHostFunction(void (*fn)(void)) { - Inst(Opcode::CallHostFunction, Imm64(Common::BitCast(fn))); + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn))); } void IREmitter::CallHostFunction(void (*fn)(u64), const U64& arg1) { - Inst(Opcode::CallHostFunction, Imm64(Common::BitCast(fn)), arg1); + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1); } void IREmitter::CallHostFunction(void (*fn)(u64, u64), const U64& arg1, const U64& arg2) { - Inst(Opcode::CallHostFunction, Imm64(Common::BitCast(fn)), arg1, arg2); + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, arg2); } void IREmitter::CallHostFunction(void (*fn)(u64, u64, u64), const U64& arg1, const U64& arg2, const U64& arg3) { - Inst(Opcode::CallHostFunction, Imm64(Common::BitCast(fn)), arg1, arg2, arg3); + Inst(Opcode::CallHostFunction, Imm64(mcl::bit_cast(fn)), arg1, arg2, arg3); } void IREmitter::SetTerm(const Terminal& terminal) { diff --git a/src/dynarmic/ir/ir_emitter.h b/src/dynarmic/ir/ir_emitter.h index fb8d957c..82b8acc0 100644 --- a/src/dynarmic/ir/ir_emitter.h +++ b/src/dynarmic/ir/ir_emitter.h @@ -5,7 +5,8 @@ #pragma once -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/ir/acc_type.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/location_descriptor.h" diff --git a/src/dynarmic/ir/location_descriptor.h b/src/dynarmic/ir/location_descriptor.h index cd47b80b..4b5d77d8 100644 --- a/src/dynarmic/ir/location_descriptor.h +++ b/src/dynarmic/ir/location_descriptor.h @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { diff --git a/src/dynarmic/ir/microinstruction.cpp b/src/dynarmic/ir/microinstruction.cpp index dae5f6ae..81bfbbaa 100644 --- a/src/dynarmic/ir/microinstruction.cpp +++ b/src/dynarmic/ir/microinstruction.cpp @@ -8,8 +8,8 @@ #include #include +#include -#include "dynarmic/common/assert.h" #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" diff --git a/src/dynarmic/ir/microinstruction.h b/src/dynarmic/ir/microinstruction.h index de3db2e5..a5011b20 100644 --- a/src/dynarmic/ir/microinstruction.h +++ b/src/dynarmic/ir/microinstruction.h @@ -7,8 +7,9 @@ #include -#include "dynarmic/common/common_types.h" -#include "dynarmic/common/intrusive_list.h" +#include +#include + #include "dynarmic/ir/value.h" namespace Dynarmic::IR { @@ -22,7 +23,7 @@ constexpr size_t max_arg_count = 4; * A representation of a microinstruction. A single ARM/Thumb instruction may be * converted into zero or more microinstructions. */ -class Inst final : public Common::IntrusiveListNode { +class Inst final : public mcl::intrusive_list_node { public: explicit Inst(Opcode op) : op(op) {} diff --git a/src/dynarmic/ir/opcodes.h b/src/dynarmic/ir/opcodes.h index 2923511d..719fda00 100644 --- a/src/dynarmic/ir/opcodes.h +++ b/src/dynarmic/ir/opcodes.h @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { diff --git a/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp b/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp index 2731037c..2689d194 100644 --- a/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp +++ b/src/dynarmic/ir/opt/a32_get_set_elimination_pass.cpp @@ -5,8 +5,9 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/frontend/A32/a32_types.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/opcodes.h" diff --git a/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp b/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp index 2248a3c1..f4920156 100644 --- a/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp +++ b/src/dynarmic/ir/opt/a64_get_set_elimination_pass.cpp @@ -5,7 +5,8 @@ #include -#include "dynarmic/common/common_types.h" +#include + #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/opcodes.h" diff --git a/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp b/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp index af4e4bef..d9b2558d 100644 --- a/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp +++ b/src/dynarmic/ir/opt/a64_merge_interpret_blocks.cpp @@ -4,8 +4,8 @@ */ #include +#include -#include "dynarmic/common/common_types.h" #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/translate/a64_translate.h" #include "dynarmic/interface/A64/config.h" diff --git a/src/dynarmic/ir/opt/constant_propagation_pass.cpp b/src/dynarmic/ir/opt/constant_propagation_pass.cpp index f4eeba0a..f30d9836 100644 --- a/src/dynarmic/ir/opt/constant_propagation_pass.cpp +++ b/src/dynarmic/ir/opt/constant_propagation_pass.cpp @@ -5,9 +5,11 @@ #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" +#include +#include +#include +#include + #include "dynarmic/common/safe_ops.h" #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/ir_emitter.h" @@ -138,13 +140,13 @@ void FoldByteReverse(IR::Inst& inst, Op op) { } if (op == Op::ByteReverseWord) { - const u32 result = Common::SwapBytes32(static_cast(operand.GetImmediateAsU64())); + const u32 result = mcl::bit::swap_bytes_32(static_cast(operand.GetImmediateAsU64())); inst.ReplaceUsesWith(IR::Value{result}); } else if (op == Op::ByteReverseHalf) { - const u16 result = Common::SwapBytes16(static_cast(operand.GetImmediateAsU64())); + const u16 result = mcl::bit::swap_bytes_16(static_cast(operand.GetImmediateAsU64())); inst.ReplaceUsesWith(IR::Value{result}); } else { - const u64 result = Common::SwapBytes64(operand.GetImmediateAsU64()); + const u64 result = mcl::bit::swap_bytes_64(operand.GetImmediateAsU64()); inst.ReplaceUsesWith(IR::Value{result}); } } @@ -237,7 +239,7 @@ void FoldMostSignificantWord(IR::Inst& inst) { const auto operand = inst.GetArg(0); if (carry_inst) { - carry_inst->ReplaceUsesWith(IR::Value{Common::Bit<31>(operand.GetImmediateAsU64())}); + carry_inst->ReplaceUsesWith(IR::Value{mcl::bit::get_bit<31>(operand.GetImmediateAsU64())}); } inst.ReplaceUsesWith(IR::Value{static_cast(operand.GetImmediateAsU64() >> 32)}); } @@ -425,12 +427,12 @@ void ConstantPropagation(IR::Block& block) { break; case Op::RotateRight32: if (FoldShifts(inst)) { - ReplaceUsesWith(inst, true, Common::RotateRight(inst.GetArg(0).GetU32(), inst.GetArg(1).GetU8())); + ReplaceUsesWith(inst, true, mcl::bit::rotate_right(inst.GetArg(0).GetU32(), inst.GetArg(1).GetU8())); } break; case Op::RotateRight64: if (FoldShifts(inst)) { - ReplaceUsesWith(inst, false, Common::RotateRight(inst.GetArg(0).GetU64(), inst.GetArg(1).GetU8())); + ReplaceUsesWith(inst, false, mcl::bit::rotate_right(inst.GetArg(0).GetU64(), inst.GetArg(1).GetU8())); } break; case Op::LogicalShiftLeftMasked32: @@ -465,12 +467,12 @@ void ConstantPropagation(IR::Block& block) { break; case Op::RotateRightMasked32: if (inst.AreAllArgsImmediates()) { - ReplaceUsesWith(inst, true, Common::RotateRight(inst.GetArg(0).GetU32(), inst.GetArg(1).GetU32())); + ReplaceUsesWith(inst, true, mcl::bit::rotate_right(inst.GetArg(0).GetU32(), inst.GetArg(1).GetU32())); } break; case Op::RotateRightMasked64: if (inst.AreAllArgsImmediates()) { - ReplaceUsesWith(inst, false, Common::RotateRight(inst.GetArg(0).GetU64(), inst.GetArg(1).GetU64())); + ReplaceUsesWith(inst, false, mcl::bit::rotate_right(inst.GetArg(0).GetU64(), inst.GetArg(1).GetU64())); } break; case Op::Add32: diff --git a/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp b/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp index 4f882077..0d0de180 100644 --- a/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp +++ b/src/dynarmic/ir/opt/dead_code_elimination_pass.cpp @@ -3,7 +3,8 @@ * SPDX-License-Identifier: 0BSD */ -#include "dynarmic/common/iterator_util.h" +#include + #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/opt/passes.h" @@ -12,7 +13,7 @@ namespace Dynarmic::Optimization { void DeadCodeElimination(IR::Block& block) { // We iterate over the instructions in reverse order. // This is because removing an instruction reduces the number of uses for earlier instructions. - for (auto& inst : Common::Reverse(block)) { + for (auto& inst : mcl::iterator::reverse(block)) { if (!inst.HasUses() && !inst.MayHaveSideEffects()) { inst.Invalidate(); } diff --git a/src/dynarmic/ir/opt/identity_removal_pass.cpp b/src/dynarmic/ir/opt/identity_removal_pass.cpp index 2b79b8a7..57d198b7 100644 --- a/src/dynarmic/ir/opt/identity_removal_pass.cpp +++ b/src/dynarmic/ir/opt/identity_removal_pass.cpp @@ -5,7 +5,8 @@ #include -#include "dynarmic/common/iterator_util.h" +#include + #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/opt/passes.h" diff --git a/src/dynarmic/ir/opt/verification_pass.cpp b/src/dynarmic/ir/opt/verification_pass.cpp index 0a391f11..8bc9e6f1 100644 --- a/src/dynarmic/ir/opt/verification_pass.cpp +++ b/src/dynarmic/ir/opt/verification_pass.cpp @@ -6,8 +6,9 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/ir/basic_block.h" #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" diff --git a/src/dynarmic/ir/terminal.h b/src/dynarmic/ir/terminal.h index 6a017e35..d437ffd5 100644 --- a/src/dynarmic/ir/terminal.h +++ b/src/dynarmic/ir/terminal.h @@ -6,8 +6,8 @@ #pragma once #include +#include -#include "dynarmic/common/common_types.h" #include "dynarmic/ir/cond.h" #include "dynarmic/ir/location_descriptor.h" diff --git a/src/dynarmic/ir/type.h b/src/dynarmic/ir/type.h index 35c02970..7f99e474 100644 --- a/src/dynarmic/ir/type.h +++ b/src/dynarmic/ir/type.h @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include namespace Dynarmic::IR { diff --git a/src/dynarmic/ir/value.cpp b/src/dynarmic/ir/value.cpp index 8cdefa39..5b86f731 100644 --- a/src/dynarmic/ir/value.cpp +++ b/src/dynarmic/ir/value.cpp @@ -5,8 +5,9 @@ #include "dynarmic/ir/value.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" +#include +#include + #include "dynarmic/ir/microinstruction.h" #include "dynarmic/ir/opcodes.h" #include "dynarmic/ir/type.h" @@ -197,11 +198,11 @@ s64 Value::GetImmediateAsS64() const { case IR::Type::U1: return s64(GetU1()); case IR::Type::U8: - return s64(Common::SignExtend<8, u64>(GetU8())); + return s64(mcl::bit::sign_extend<8, u64>(GetU8())); case IR::Type::U16: - return s64(Common::SignExtend<16, u64>(GetU16())); + return s64(mcl::bit::sign_extend<16, u64>(GetU16())); case IR::Type::U32: - return s64(Common::SignExtend<32, u64>(GetU32())); + return s64(mcl::bit::sign_extend<32, u64>(GetU32())); case IR::Type::U64: return s64(GetU64()); default: diff --git a/src/dynarmic/ir/value.h b/src/dynarmic/ir/value.h index 9e0b19c7..122d86e5 100644 --- a/src/dynarmic/ir/value.h +++ b/src/dynarmic/ir/value.h @@ -8,8 +8,9 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/ir/type.h" namespace Dynarmic::A32 { diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp index ccc3d46b..bd53af15 100644 --- a/tests/A32/fuzz_arm.cpp +++ b/tests/A32/fuzz_arm.cpp @@ -11,16 +11,18 @@ #include #include +#include +#include +#include +#include #include "../fuzz_util.h" #include "../rand_int.h" #include "../unicorn_emu/a32_unicorn.h" #include "./testenv.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/llvm_disassemble.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/frontend/A32/ITState.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/a32_types.h" @@ -255,7 +257,7 @@ std::vector GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s const u32 inst = instructions.generators[index].Generate(); const bool is_four_bytes = (inst >> 16) != 0; - if (ShouldTestInst(is_four_bytes ? Common::SwapHalves32(inst) : inst, pc, true, is_last_inst, it_state)) { + if (ShouldTestInst(is_four_bytes ? mcl::bit::swap_halves_32(inst) : inst, pc, true, is_last_inst, it_state)) { if (is_four_bytes) return {static_cast(inst >> 16), static_cast(inst)}; return {static_cast(inst)}; @@ -625,7 +627,7 @@ TEST_CASE("A32: Test thumb IT instruction", "[thumb]") { A32::ITState it_state = [&] { while (true) { const u16 imm8 = RandInt(0, 0xFF); - if (Common::Bits<0, 3>(imm8) == 0b0000 || Common::Bits<4, 7>(imm8) == 0b1111 || (Common::Bits<4, 7>(imm8) == 0b1110 && Common::BitCount(Common::Bits<0, 3>(imm8)) != 1)) { + if (mcl::bit::get_bits<0, 3>(imm8) == 0b0000 || mcl::bit::get_bits<4, 7>(imm8) == 0b1111 || (mcl::bit::get_bits<4, 7>(imm8) == 0b1110 && mcl::bit::count_ones(mcl::bit::get_bits<0, 3>(imm8)) != 1)) { continue; } instructions.push_back(0b1011111100000000 | imm8); diff --git a/tests/A32/fuzz_thumb.cpp b/tests/A32/fuzz_thumb.cpp index a7b04a57..d412b97e 100644 --- a/tests/A32/fuzz_thumb.cpp +++ b/tests/A32/fuzz_thumb.cpp @@ -13,12 +13,12 @@ #include #include +#include +#include #include "../rand_int.h" #include "../unicorn_emu/a32_unicorn.h" #include "./testenv.h" -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/frontend/A32/FPSCR.h" #include "dynarmic/frontend/A32/PSR.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" @@ -236,8 +236,8 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to for (size_t i = 0; i < instruction_count; i++) { const auto instruction = instruction_generator(); - const auto first_halfword = static_cast(Common::Bits<0, 15>(instruction)); - const auto second_halfword = static_cast(Common::Bits<16, 31>(instruction)); + const auto first_halfword = static_cast(mcl::bit::get_bits<0, 15>(instruction)); + const auto second_halfword = static_cast(mcl::bit::get_bits<16, 31>(instruction)); test_env.code_mem[i * 2 + 0] = second_halfword; test_env.code_mem[i * 2 + 1] = first_halfword; @@ -249,39 +249,39 @@ void FuzzJitThumb32(const size_t instruction_count, const size_t instructions_to TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb][Thumb16]") { const std::array instructions = { - ThumbInstGen("00000xxxxxxxxxxx"), // LSL , , # - ThumbInstGen("00001xxxxxxxxxxx"), // LSR , , # - ThumbInstGen("00010xxxxxxxxxxx"), // ASR , , # - ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg - ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm - ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm - ThumbInstGen("010000ooooxxxxxx"), // Data Processing - ThumbInstGen("010001000hxxxxxx"), // ADD (high registers) - ThumbInstGen("0100010101xxxxxx", // CMP (high registers) - [](u32 inst) { return Common::Bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE - ThumbInstGen("0100010110xxxxxx", // CMP (high registers) - [](u32 inst) { return Common::Bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE - ThumbInstGen("010001100hxxxxxx"), // MOV (high registers) - ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer - ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT - ThumbInstGen("1011101000xxxxxx"), // REV - ThumbInstGen("1011101001xxxxxx"), // REV16 - ThumbInstGen("1011101011xxxxxx"), // REVSH - ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #] - ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm] - ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #] - ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset] - ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #] - ThumbInstGen("1011010xxxxxxxxx", // PUSH - [](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE - ThumbInstGen("10111100xxxxxxxx", // POP (P = 0) - [](u32 inst) { return Common::Bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE - ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA + ThumbInstGen("00000xxxxxxxxxxx"), // LSL , , # + ThumbInstGen("00001xxxxxxxxxxx"), // LSR , , # + ThumbInstGen("00010xxxxxxxxxxx"), // ASR , , # + ThumbInstGen("000110oxxxxxxxxx"), // ADD/SUB_reg + ThumbInstGen("000111oxxxxxxxxx"), // ADD/SUB_imm + ThumbInstGen("001ooxxxxxxxxxxx"), // ADD/SUB/CMP/MOV_imm + ThumbInstGen("010000ooooxxxxxx"), // Data Processing + ThumbInstGen("010001000hxxxxxx"), // ADD (high registers) + ThumbInstGen("0100010101xxxxxx", // CMP (high registers) + [](u32 inst) { return mcl::bit::get_bits<3, 5>(inst) != 0b111; }), // R15 is UNPREDICTABLE + ThumbInstGen("0100010110xxxxxx", // CMP (high registers) + [](u32 inst) { return mcl::bit::get_bits<0, 2>(inst) != 0b111; }), // R15 is UNPREDICTABLE + ThumbInstGen("010001100hxxxxxx"), // MOV (high registers) + ThumbInstGen("10110000oxxxxxxx"), // Adjust stack pointer + ThumbInstGen("10110010ooxxxxxx"), // SXT/UXT + ThumbInstGen("1011101000xxxxxx"), // REV + ThumbInstGen("1011101001xxxxxx"), // REV16 + ThumbInstGen("1011101011xxxxxx"), // REVSH + ThumbInstGen("01001xxxxxxxxxxx"), // LDR Rd, [PC, #] + ThumbInstGen("0101oooxxxxxxxxx"), // LDR/STR Rd, [Rn, Rm] + ThumbInstGen("011xxxxxxxxxxxxx"), // LDR(B)/STR(B) Rd, [Rn, #] + ThumbInstGen("1000xxxxxxxxxxxx"), // LDRH/STRH Rd, [Rn, #offset] + ThumbInstGen("1001xxxxxxxxxxxx"), // LDR/STR Rd, [SP, #] + ThumbInstGen("1011010xxxxxxxxx", // PUSH + [](u32 inst) { return mcl::bit::get_bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE + ThumbInstGen("10111100xxxxxxxx", // POP (P = 0) + [](u32 inst) { return mcl::bit::get_bits<0, 7>(inst) != 0; }), // Empty reg_list is UNPREDICTABLE + ThumbInstGen("1100xxxxxxxxxxxx", // STMIA/LDMIA [](u32 inst) { // Ensure that the architecturally undefined case of // the base register being within the list isn't hit. - const u32 rn = Common::Bits<8, 10>(inst); - return (inst & (1U << rn)) == 0 && Common::Bits<0, 7>(inst) != 0; + const u32 rn = mcl::bit::get_bits<8, 10>(inst); + return (inst & (1U << rn)) == 0 && mcl::bit::get_bits<0, 7>(inst) != 0; }), // TODO: We should properly test against swapped // endianness cases, however Unicorn doesn't @@ -325,7 +325,7 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16 #if 0 ThumbInstGen("01000111xmmmm000", // BLX/BX [](u32 inst){ - const u32 Rm = Common::Bits<3, 6>(inst); + const u32 Rm = mcl::bit::get_bits<3, 6>(inst); return Rm != 15; }), #endif @@ -335,7 +335,7 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16 ThumbInstGen("01000110h0xxxxxx"), // MOV (high registers) ThumbInstGen("1101ccccxxxxxxxx", // B [](u32 inst) { - const u32 c = Common::Bits<9, 12>(inst); + const u32 c = mcl::bit::get_bits<9, 12>(inst); return c < 0b1110; // Don't want SWI or undefined instructions. }), ThumbInstGen("1011o0i1iiiiinnn"), // CBZ/CBNZ @@ -360,18 +360,18 @@ TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb][Thumb16 TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { const auto three_reg_not_r15 = [](u32 inst) { - const auto d = Common::Bits<8, 11>(inst); - const auto m = Common::Bits<0, 3>(inst); - const auto n = Common::Bits<16, 19>(inst); + const auto d = mcl::bit::get_bits<8, 11>(inst); + const auto m = mcl::bit::get_bits<0, 3>(inst); + const auto n = mcl::bit::get_bits<16, 19>(inst); return d != 15 && m != 15 && n != 15; }; const std::array instructions = { ThumbInstGen("111110101011nnnn1111dddd1000mmmm", // CLZ [](u32 inst) { - const auto d = Common::Bits<8, 11>(inst); - const auto m = Common::Bits<0, 3>(inst); - const auto n = Common::Bits<16, 19>(inst); + const auto d = mcl::bit::get_bits<8, 11>(inst); + const auto m = mcl::bit::get_bits<0, 3>(inst); + const auto n = mcl::bit::get_bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), ThumbInstGen("111110101000nnnn1111dddd1000mmmm", // QADD @@ -396,30 +396,30 @@ TEST_CASE("Fuzz Thumb32 instructions set", "[JitX64][Thumb][Thumb32]") { three_reg_not_r15), ThumbInstGen("111110101001nnnn1111dddd1010mmmm", // RBIT [](u32 inst) { - const auto d = Common::Bits<8, 11>(inst); - const auto m = Common::Bits<0, 3>(inst); - const auto n = Common::Bits<16, 19>(inst); + const auto d = mcl::bit::get_bits<8, 11>(inst); + const auto m = mcl::bit::get_bits<0, 3>(inst); + const auto n = mcl::bit::get_bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), ThumbInstGen("111110101001nnnn1111dddd1000mmmm", // REV [](u32 inst) { - const auto d = Common::Bits<8, 11>(inst); - const auto m = Common::Bits<0, 3>(inst); - const auto n = Common::Bits<16, 19>(inst); + const auto d = mcl::bit::get_bits<8, 11>(inst); + const auto m = mcl::bit::get_bits<0, 3>(inst); + const auto n = mcl::bit::get_bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), ThumbInstGen("111110101001nnnn1111dddd1001mmmm", // REV16 [](u32 inst) { - const auto d = Common::Bits<8, 11>(inst); - const auto m = Common::Bits<0, 3>(inst); - const auto n = Common::Bits<16, 19>(inst); + const auto d = mcl::bit::get_bits<8, 11>(inst); + const auto m = mcl::bit::get_bits<0, 3>(inst); + const auto n = mcl::bit::get_bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), ThumbInstGen("111110101001nnnn1111dddd1011mmmm", // REVSH [](u32 inst) { - const auto d = Common::Bits<8, 11>(inst); - const auto m = Common::Bits<0, 3>(inst); - const auto n = Common::Bits<16, 19>(inst); + const auto d = mcl::bit::get_bits<8, 11>(inst); + const auto m = mcl::bit::get_bits<0, 3>(inst); + const auto n = mcl::bit::get_bits<16, 19>(inst); return m == n && d != 15 && m != 15; }), ThumbInstGen("111110101000nnnn1111dddd0000mmmm", // SADD8 diff --git a/tests/A32/test_thumb_instructions.cpp b/tests/A32/test_thumb_instructions.cpp index 734836a6..c403f8bb 100644 --- a/tests/A32/test_thumb_instructions.cpp +++ b/tests/A32/test_thumb_instructions.cpp @@ -4,9 +4,9 @@ */ #include +#include #include "./testenv.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/interface/A32/a32.h" static Dynarmic::A32::UserConfig GetUserConfig(ThumbTestEnv* testenv) { diff --git a/tests/A32/testenv.h b/tests/A32/testenv.h index 68538ba2..ac7921ec 100644 --- a/tests/A32/testenv.h +++ b/tests/A32/testenv.h @@ -11,8 +11,9 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/interface/A32/a32.h" template diff --git a/tests/A64/fuzz_with_unicorn.cpp b/tests/A64/fuzz_with_unicorn.cpp index 433f8ca9..0307751c 100644 --- a/tests/A64/fuzz_with_unicorn.cpp +++ b/tests/A64/fuzz_with_unicorn.cpp @@ -9,16 +9,16 @@ #include #include +#include +#include #include "../fuzz_util.h" #include "../rand_int.h" #include "../unicorn_emu/a64_unicorn.h" #include "./testenv.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/llvm_disassemble.h" -#include "dynarmic/common/scope_exit.h" #include "dynarmic/frontend/A64/a64_location_descriptor.h" #include "dynarmic/frontend/A64/a64_types.h" #include "dynarmic/frontend/A64/decoder/a64.h" diff --git a/tests/A64/testenv.h b/tests/A64/testenv.h index d18797f2..596d0114 100644 --- a/tests/A64/testenv.h +++ b/tests/A64/testenv.h @@ -8,8 +8,9 @@ #include #include -#include "dynarmic/common/assert.h" -#include "dynarmic/common/common_types.h" +#include +#include + #include "dynarmic/interface/A64/a64.h" using Vector = Dynarmic::A64::Vector; diff --git a/tests/decoder_tests.cpp b/tests/decoder_tests.cpp index b4b12273..519d2b17 100644 --- a/tests/decoder_tests.cpp +++ b/tests/decoder_tests.cpp @@ -8,8 +8,8 @@ #include #include +#include -#include "dynarmic/common/assert.h" #include "dynarmic/frontend/A32/decoder/asimd.h" #include "dynarmic/frontend/A32/translate/impl/a32_translate_impl.h" #include "dynarmic/interface/A32/config.h" diff --git a/tests/fp/FPToFixed.cpp b/tests/fp/FPToFixed.cpp index 354ab483..9375003f 100644 --- a/tests/fp/FPToFixed.cpp +++ b/tests/fp/FPToFixed.cpp @@ -7,9 +7,9 @@ #include #include +#include #include "../rand_int.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/op.h" diff --git a/tests/fp/mantissa_util_tests.cpp b/tests/fp/mantissa_util_tests.cpp index ce833ff6..76311f1f 100644 --- a/tests/fp/mantissa_util_tests.cpp +++ b/tests/fp/mantissa_util_tests.cpp @@ -7,9 +7,9 @@ #include #include +#include #include "../rand_int.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/mantissa_util.h" #include "dynarmic/common/safe_ops.h" @@ -37,7 +37,7 @@ TEST_CASE("ResidualErrorOnRightShift", "[fp]") { TEST_CASE("ResidualErrorOnRightShift Randomized", "[fp]") { for (size_t test = 0; test < 100000; test++) { - const u64 mantissa = Common::SignExtend<32, u64>(RandInt(0, 0xFFFFFFFF)); + const u64 mantissa = mcl::bit::sign_extend<32, u64>(RandInt(0, 0xFFFFFFFF)); const int shift = RandInt(-60, 60); const ResidualError result = ResidualErrorOnRightShift(mantissa, shift); diff --git a/tests/fp/unpacked_tests.cpp b/tests/fp/unpacked_tests.cpp index d201e7ec..d61f514f 100644 --- a/tests/fp/unpacked_tests.cpp +++ b/tests/fp/unpacked_tests.cpp @@ -7,9 +7,9 @@ #include #include +#include #include "../rand_int.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/unpacked.h" diff --git a/tests/fuzz_util.cpp b/tests/fuzz_util.cpp index 1de6c29f..12dc850b 100644 --- a/tests/fuzz_util.cpp +++ b/tests/fuzz_util.cpp @@ -9,9 +9,9 @@ #include #include +#include #include "./rand_int.h" -#include "dynarmic/common/assert.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/rounding_mode.h" diff --git a/tests/fuzz_util.h b/tests/fuzz_util.h index 04334272..95303077 100644 --- a/tests/fuzz_util.h +++ b/tests/fuzz_util.h @@ -8,7 +8,7 @@ #include #include -#include "dynarmic/common/common_types.h" +#include using Vector = std::array; diff --git a/tests/print_info.cpp b/tests/print_info.cpp index c20ac371..d7978fd8 100644 --- a/tests/print_info.cpp +++ b/tests/print_info.cpp @@ -14,9 +14,9 @@ #include #include +#include +#include -#include "dynarmic/common/bit_util.h" -#include "dynarmic/common/common_types.h" #include "dynarmic/common/llvm_disassemble.h" #include "dynarmic/frontend/A32/a32_location_descriptor.h" #include "dynarmic/frontend/A32/decoder/arm.h" @@ -98,7 +98,7 @@ void PrintA64Instruction(u32 instruction) { void PrintThumbInstruction(u32 instruction) { const size_t inst_size = (instruction >> 16) == 0 ? 2 : 4; if (inst_size == 4) - instruction = Common::SwapHalves32(instruction); + instruction = mcl::bit::swap_halves_32(instruction); fmt::print("{:08x} {}\n", instruction, Common::DisassembleAArch32(true, 0, (u8*)&instruction, inst_size)); diff --git a/tests/rsqrt_test.cpp b/tests/rsqrt_test.cpp index f367da87..cb49ca0c 100644 --- a/tests/rsqrt_test.cpp +++ b/tests/rsqrt_test.cpp @@ -5,8 +5,8 @@ #include #include +#include -#include "dynarmic/common/common_types.h" #include "dynarmic/common/fp/fpcr.h" #include "dynarmic/common/fp/fpsr.h" #include "dynarmic/common/fp/op/FPRSqrtEstimate.h" diff --git a/tests/unicorn_emu/a32_unicorn.cpp b/tests/unicorn_emu/a32_unicorn.cpp index d9a68662..f3ffa0da 100644 --- a/tests/unicorn_emu/a32_unicorn.cpp +++ b/tests/unicorn_emu/a32_unicorn.cpp @@ -7,9 +7,10 @@ #include +#include +#include + #include "../A32/testenv.h" -#include "dynarmic/common/assert.h" -#include "dynarmic/common/bit_util.h" #define CHECKED(expr) \ do { \ @@ -60,7 +61,7 @@ void A32Unicorn::Run() { } } - const bool T = Dynarmic::Common::Bit<5>(GetCpsr()); + const bool T = mcl::bit::get_bit<5>(GetCpsr()); const u32 new_pc = GetPC() | (T ? 1 : 0); SetPC(new_pc); } @@ -262,7 +263,7 @@ void A32Unicorn::InterruptHook(uc_engine* /*uc*/, u32 int_numbe auto* this_ = static_cast(user_data); u32 esr = 0; - //CHECKED(uc_reg_read(uc, UC_ARM_REG_ESR, &esr)); + // CHECKED(uc_reg_read(uc, UC_ARM_REG_ESR, &esr)); auto ec = esr >> 26; auto iss = esr & 0xFFFFFF; diff --git a/tests/unicorn_emu/a32_unicorn.h b/tests/unicorn_emu/a32_unicorn.h index 1cf06a02..d4fe3c41 100644 --- a/tests/unicorn_emu/a32_unicorn.h +++ b/tests/unicorn_emu/a32_unicorn.h @@ -16,8 +16,9 @@ # include #endif +#include + #include "../A32/testenv.h" -#include "dynarmic/common/common_types.h" namespace Unicorn::A32 { static constexpr size_t num_gprs = 16; diff --git a/tests/unicorn_emu/a64_unicorn.cpp b/tests/unicorn_emu/a64_unicorn.cpp index 583e04d9..f4e14b25 100644 --- a/tests/unicorn_emu/a64_unicorn.cpp +++ b/tests/unicorn_emu/a64_unicorn.cpp @@ -5,7 +5,7 @@ #include "./a64_unicorn.h" -#include "dynarmic/common/assert.h" +#include #define CHECKED(expr) \ do { \ diff --git a/tests/unicorn_emu/a64_unicorn.h b/tests/unicorn_emu/a64_unicorn.h index 580c88a0..57759605 100644 --- a/tests/unicorn_emu/a64_unicorn.h +++ b/tests/unicorn_emu/a64_unicorn.h @@ -16,8 +16,9 @@ # include #endif +#include + #include "../A64/testenv.h" -#include "dynarmic/common/common_types.h" class A64Unicorn final { public: