Merge pull request #577 from lioncash/barrier
thumb32: Implement barrier instructions and CLREX
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commit
75f4978da5
3 changed files with 30 additions and 4 deletions
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@ -106,10 +106,10 @@ INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiidd
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//INST(thumb32_ENTERX, "ENTERX", "111100111011----10-0----0001----")
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//INST(thumb32_LEAVEX, "LEAVEX", "111100111011----10-0----0000----")
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//INST(thumb32_CLREX, "CLREX", "111100111011----10-0----0010----")
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//INST(thumb32_DSB, "DSB", "111100111011----10-0----0100----")
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//INST(thumb32_DMB, "DMB", "111100111011----10-0----0101----")
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//INST(thumb32_ISB, "ISB", "111100111011----10-0----0110----")
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INST(thumb32_CLREX, "CLREX", "11110011101111111000111100101111")
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INST(thumb32_DSB, "DSB", "1111001110111111100011110100oooo")
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INST(thumb32_DMB, "DMB", "1111001110111111100011110101oooo")
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INST(thumb32_ISB, "ISB", "1111001110111111100011110110oooo")
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//INST(thumb32_BXJ, "BXJ", "111100111100----1000111100000000")
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//INST(thumb32_ERET, "ERET", "11110011110111101000111100000000")
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@ -7,6 +7,28 @@
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namespace Dynarmic::A32 {
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bool ThumbTranslatorVisitor::thumb32_CLREX() {
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ir.ClearExclusive();
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_DMB([[maybe_unused]] Imm<4> option) {
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ir.DataMemoryBarrier();
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_DSB([[maybe_unused]] Imm<4> option) {
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ir.DataSynchronizationBarrier();
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_ISB([[maybe_unused]] Imm<4> option) {
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ir.InstructionSynchronizationBarrier();
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ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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bool ThumbTranslatorVisitor::thumb32_UDF() {
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return thumb16_UDF();
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}
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@ -164,6 +164,10 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
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// thumb32 miscellaneous control instructions
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bool thumb32_CLREX();
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bool thumb32_DMB(Imm<4> option);
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bool thumb32_DSB(Imm<4> option);
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bool thumb32_ISB(Imm<4> option);
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bool thumb32_UDF();
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// thumb32 branch instructions
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