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thumb32: Implement BFC/BFI

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This commit is contained in:
Lioncash 2021-02-25 09:20:55 -05:00
parent ba7cbe7cf6
commit 7334914047
3 changed files with 46 additions and 2 deletions
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4
src/frontend/A32/decoder/thumb32.inc
View file

@ -81,8 +81,8 @@ INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiidd
INST(thumb32_SSAT16, "SSAT16", "111100110010nnnn0000dddd0000iiii")
//INST(thumb32_SSAT, "SSAT", "11110-110010----0---------------")
//INST(thumb32_SBFX, "SBFX", "11110-110100----0---------------")
//INST(thumb32_BFC, "BFC", "11110-11011011110---------------")
//INST(thumb32_BFI, "BFI", "11110-110110----0---------------")
INST(thumb32_BFC, "BFC", "11110011011011110iiiddddii0bbbbb")
INST(thumb32_BFI, "BFI", "111100110110nnnn0iiiddddii0bbbbb")
//INST(thumb32_USAT, "USAT", "11110-111000----0---------------")
INST(thumb32_USAT16, "USAT16", "111100111010nnnn0000dddd0000iiii")
//INST(thumb32_USAT, "USAT", "11110-111010----0---------------")

42
src/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp
View file

@ -34,6 +34,48 @@ static bool Saturation16(ThumbTranslatorVisitor& v, Reg n, Reg d, size_t saturat
return true;
}
bool ThumbTranslatorVisitor::thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) {
if (d == Reg::PC) {
return UnpredictableInstruction();
}
const u32 lsbit = concatenate(imm3, imm2).ZeroExtend();
const u32 msbit = msb.ZeroExtend();
if (msbit < lsbit) {
return UnpredictableInstruction();
}
const u32 mask = ~(Common::Ones<u32>(msbit - lsbit + 1) << lsbit);
const auto reg_d = ir.GetRegister(d);
const auto result = ir.And(reg_d, ir.Imm32(mask));
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb) {
if (d == Reg::PC || n == Reg::PC) {
return UnpredictableInstruction();
}
const u32 lsbit = concatenate(imm3, imm2).ZeroExtend();
const u32 msbit = msb.ZeroExtend();
if (msbit < lsbit) {
return UnpredictableInstruction();
}
const u32 inclusion_mask = Common::Ones<u32>(msbit - lsbit + 1) << lsbit;
const u32 exclusion_mask = ~inclusion_mask;
const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask));
const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(u8(lsbit))), ir.Imm32(inclusion_mask));
const IR::U32 result = ir.Or(operand1, operand2);
ir.SetRegister(d, result);
return true;
}
bool ThumbTranslatorVisitor::thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC) {
return UnpredictableInstruction();

2
src/frontend/A32/translate/impl/translate_thumb.h
View file

@ -160,6 +160,8 @@ struct ThumbTranslatorVisitor final {
bool thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
// thumb32 data processing (plain binary immediate) instructions.
bool thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
bool thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_MOVW_imm(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm);