From 6f9216d5440b486ee328b7e042542b8ab76f8f23 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Tue, 23 Jan 2018 19:13:47 -0500
Subject: [PATCH] A64: Implement RBIT

---
 src/frontend/A64/decoder/a64.inc              |  2 +-
 .../impl/data_processing_register.cpp         | 41 +++++++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index c540209f..2ba49e70 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -285,7 +285,7 @@ INST(RORV,                   "RORV",                                      "z0011
 //INST(PACGA,                  "PACGA",                                     "10011010110mmmmm001100nnnnnddddd")
 
 // Data Processing - Register - 1 source
-//INST(RBIT_int,               "RBIT",                                      "z101101011000000000000nnnnnddddd")
+INST(RBIT_int,               "RBIT",                                      "z101101011000000000000nnnnnddddd")
 INST(REV16_int,              "REV16",                                     "z101101011000000000001nnnnnddddd")
 INST(REV,                    "REV",                                       "z10110101100000000001onnnnnddddd")
 INST(CLZ_int,                "CLZ",                                       "z101101011000000000100nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/data_processing_register.cpp b/src/frontend/A64/translate/impl/data_processing_register.cpp
index e3afcb61..b7a20a9c 100644
--- a/src/frontend/A64/translate/impl/data_processing_register.cpp
+++ b/src/frontend/A64/translate/impl/data_processing_register.cpp
@@ -29,6 +29,47 @@ bool TranslatorVisitor::CLS_int(bool sf, Reg Rn, Reg Rd) {
     return true;
 }
 
+bool TranslatorVisitor::RBIT_int(bool sf, Reg Rn, Reg Rd) {
+    const auto rbit32 = [this](const IR::U32& operand) {
+        // x = (x & 0x55555555) << 1 | ((x >> 1) & 0x55555555);
+        const IR::U32 first_lsl = ir.LogicalShiftLeft(ir.And(operand, ir.Imm32(0x55555555)), ir.Imm8(1));
+        const IR::U32 first_lsr = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(1)), ir.Imm32(0x55555555));
+        const IR::U32 first = ir.Or(first_lsl, first_lsr);
+        
+        // x = (x & 0x33333333) << 2 | ((x >> 2) & 0x33333333);
+        const IR::U32 second_lsl = ir.LogicalShiftLeft(ir.And(first, ir.Imm32(0x33333333)), ir.Imm8(2));
+        const IR::U32 second_lsr = ir.And(ir.LogicalShiftRight(first, ir.Imm8(2)), ir.Imm32(0x33333333));
+        const IR::U32 second = ir.Or(second_lsl, second_lsr);
+        
+        // x = (x & 0x0F0F0F0F) << 4 | ((x >> 4) & 0x0F0F0F0F);
+        const IR::U32 third_lsl = ir.LogicalShiftLeft(ir.And(second, ir.Imm32(0x0F0F0F0F)), ir.Imm8(4));
+        const IR::U32 third_lsr = ir.And(ir.LogicalShiftRight(second, ir.Imm8(4)), ir.Imm32(0x0F0F0F0F));
+        const IR::U32 third = ir.Or(third_lsl, third_lsr);
+        
+        // x = (x << 24) | ((x & 0xFF00) << 8) | ((x >> 8) & 0xFF00) | (x >> 24);
+        const IR::U32 fourth_lsl = ir.Or(ir.LogicalShiftLeft(third, ir.Imm8(24)),
+                                         ir.LogicalShiftLeft(ir.And(third, ir.Imm32(0xFF00)), ir.Imm8(8)));
+        const IR::U32 fourth_lsr = ir.Or(ir.And(ir.LogicalShiftRight(third, ir.Imm8(8)), ir.Imm32(0xFF00)),
+                                         ir.LogicalShiftRight(third, ir.Imm8(24)));
+        return ir.Or(fourth_lsl, fourth_lsr);
+    };
+
+    const size_t datasize = sf ? 64 : 32;
+    const IR::U32U64 operand = X(datasize, Rn);
+
+    if (sf) {
+        const IR::U32 lsw = rbit32(ir.LeastSignificantWord(operand));
+        const IR::U32 msw = rbit32(ir.MostSignificantWord(operand).result);
+        const IR::U64 result = ir.Pack2x32To1x64(msw, lsw);
+
+        X(datasize, Rd, result);
+    } else {
+        X(datasize, Rd, rbit32(operand));
+    }
+
+    return true;
+}
+
 bool TranslatorVisitor::REV(bool sf, bool opc_0, Reg Rn, Reg Rd) {
     const size_t datasize = sf ? 64 : 32;