diff --git a/src/frontend/A32/decoder/arm.inc b/src/frontend/A32/decoder/arm.inc
index 5c147d8a..3237b480 100644
--- a/src/frontend/A32/decoder/arm.inc
+++ b/src/frontend/A32/decoder/arm.inc
@@ -121,6 +121,7 @@ INST(arm_SWPB,          "SWPB",                "cccc00010100nnnntttt00001001uuuu
 INST(arm_LDRBT,         "LDRBT (A1)",          "----0100-111--------------------")
 INST(arm_LDRBT,         "LDRBT (A2)",          "----0110-111---------------0----")
 INST(arm_LDRHT,         "LDRHT (A1)",          "----0000-111------------1011----")
+INST(arm_LDRHT,         "LDRHT (A1)",          "----0000-1111111--------1011----")
 INST(arm_LDRHT,         "LDRHT (A2)",          "----0000-011--------00001011----")
 INST(arm_LDRSBT,        "LDRSBT (A1)",         "----0000-111------------1101----")
 INST(arm_LDRSBT,        "LDRSBT (A2)",         "----0000-011--------00001101----")
diff --git a/src/frontend/A32/decoder/vfp.inc b/src/frontend/A32/decoder/vfp.inc
index ee3ba253..70a42a42 100644
--- a/src/frontend/A32/decoder/vfp.inc
+++ b/src/frontend/A32/decoder/vfp.inc
@@ -49,6 +49,7 @@ INST(vfp_VPUSH,            "VPUSH",                   "cccc11010D101101dddd101zv
 INST(vfp_VPOP,             "VPOP",                    "cccc11001D111101dddd101zvvvvvvvv") // VFPv2
 INST(vfp_VLDR,             "VLDR",                    "cccc1101UD01nnnndddd101zvvvvvvvv") // VFPv2
 INST(vfp_VSTR,             "VSTR",                    "cccc1101UD00nnnndddd101zvvvvvvvv") // VFPv2
+INST(arm_UDF,              "Undefined VSTM/VLDM",     "----11000-0---------101---------") // VFPv2
 INST(vfp_VSTM_a1,          "VSTM (A1)",               "cccc110puDw0nnnndddd1011vvvvvvvv") // VFPv2
 INST(vfp_VSTM_a2,          "VSTM (A2)",               "cccc110puDw0nnnndddd1010vvvvvvvv") // VFPv2
 INST(vfp_VLDM_a1,          "VLDM (A1)",               "cccc110puDw1nnnndddd1011vvvvvvvv") // VFPv2
diff --git a/src/frontend/A32/translate/impl/load_store.cpp b/src/frontend/A32/translate/impl/load_store.cpp
index 727e015e..f1e1319c 100644
--- a/src/frontend/A32/translate/impl/load_store.cpp
+++ b/src/frontend/A32/translate/impl/load_store.cpp
@@ -8,35 +8,43 @@
 namespace Dynarmic::A32 {
 
 bool ArmTranslatorVisitor::arm_LDRBT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_LDRHT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_LDRSBT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_LDRSHT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_LDRT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_STRBT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_STRHT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 bool ArmTranslatorVisitor::arm_STRT() {
-    ASSERT_FALSE("System instructions unimplemented");
+    // System instructions unimplemented
+    return UndefinedInstruction();
 }
 
 static IR::U32 GetAddress(A32::IREmitter& ir, bool P, bool U, bool W, Reg n, IR::U32 offset) {
diff --git a/src/frontend/A32/translate/impl/vfp.cpp b/src/frontend/A32/translate/impl/vfp.cpp
index 82dec2db..1e1b991f 100644
--- a/src/frontend/A32/translate/impl/vfp.cpp
+++ b/src/frontend/A32/translate/impl/vfp.cpp
@@ -643,7 +643,9 @@ bool ArmTranslatorVisitor::vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8
         return true;
     }
 
+    const u32 imm32 = imm8.ZeroExtend() << 2;
     auto address = ir.GetRegister(Reg::SP);
+    ir.SetRegister(Reg::SP, ir.Add(address, ir.Imm32(imm32)));
 
     for (size_t i = 0; i < regs; ++i) {
         if (sz) {
@@ -662,7 +664,6 @@ bool ArmTranslatorVisitor::vfp_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm<8
         }
     }
 
-    ir.SetRegister(Reg::SP, address);
     return true;
 }
 
diff --git a/tests/A32/fuzz_arm.cpp b/tests/A32/fuzz_arm.cpp
index f977a658..0aeee4fd 100644
--- a/tests/A32/fuzz_arm.cpp
+++ b/tests/A32/fuzz_arm.cpp
@@ -123,9 +123,10 @@ u32 GenRandomInst(u32 pc, bool is_last_inst) {
         const size_t index = RandInt<size_t>(0, instructions.generators.size() - 1);
         const u32 inst = instructions.generators[index].Generate();
 
-        if (std::any_of(instructions.invalid.begin(), instructions.invalid.end(), [inst](const auto& invalid) { return invalid.Match(inst); })) {
+        if ((instructions.generators[index].Mask() & 0xF0000000) == 0 && (inst & 0xF0000000) == 0xF0000000) {
             continue;
         }
+
         if (ShouldTestInst(inst, pc, is_last_inst)) {
             return inst;
         }