diff --git a/src/dynarmic/backend/arm64/emit_arm64_a64.cpp b/src/dynarmic/backend/arm64/emit_arm64_a64.cpp
index df593085..17bc8cc9 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_a64.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_a64.cpp
@@ -385,14 +385,14 @@ void EmitIR<IR::Opcode::A64ExceptionRaised>(oaknut::CodeGenerator& code, EmitCon
 template<>
 void EmitIR<IR::Opcode::A64DataCacheOperationRaised>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ctx.reg_alloc.PrepareForCall(nullptr, args[1], args[2]);
+    ctx.reg_alloc.PrepareForCall(nullptr, {}, args[1], args[2]);
     EmitRelocation(code, ctx, LinkTarget::DataCacheOperationRaised);
 }
 
 template<>
 void EmitIR<IR::Opcode::A64InstructionCacheOperationRaised>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
     auto args = ctx.reg_alloc.GetArgumentInfo(inst);
-    ctx.reg_alloc.PrepareForCall(nullptr, args[1], args[2]);
+    ctx.reg_alloc.PrepareForCall(nullptr, {}, args[0], args[1]);
     EmitRelocation(code, ctx, LinkTarget::InstructionCacheOperationRaised);
 }
 
diff --git a/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp b/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
index 9f632c24..087499ce 100644
--- a/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
+++ b/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
@@ -11,6 +11,7 @@
 #include "dynarmic/backend/arm64/emit_context.h"
 #include "dynarmic/backend/arm64/fpsr_manager.h"
 #include "dynarmic/backend/arm64/reg_alloc.h"
+#include "dynarmic/common/fp/info.h"
 #include "dynarmic/ir/basic_block.h"
 #include "dynarmic/ir/microinstruction.h"
 #include "dynarmic/ir/opcodes.h"
@@ -234,10 +235,17 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
 
 template<>
 void EmitIR<IR::Opcode::FPVectorAbs16>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    (void)code;
-    (void)ctx;
-    (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    constexpr u16 non_sign_mask = FP::FPInfo<u16>::sign_mask - u16{1u};
+    constexpr u64 non_sign_mask64 = mcl::bit::replicate_element<16, u64>(non_sign_mask);
+
+    auto args = ctx.reg_alloc.GetArgumentInfo(inst);
+    auto Qoperand = ctx.reg_alloc.ReadQ(args[0]);
+    auto Qresult = ctx.reg_alloc.WriteQ(inst);
+    RegAlloc::Realize(Qoperand, Qresult);
+
+    code.MOV(Xscratch0, non_sign_mask64);
+    code.DUP(Qresult->D2(), Xscratch0);
+    code.AND(Qresult->B16(), Qoperand->B16(), Qresult->B16());
 }
 
 template<>