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A64: Implement REV16 (vector)

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Lioncash 2018-03-15 16:59:48 -04:00 committed by MerryMage
parent 6177c2c63d
commit 6ad1bce5e0
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -566,7 +566,7 @@ INST(INS_elt, "INS (element)", "01101
// Data Processing - FP and SIMD - SIMD Two-register misc
//INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd")
//INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd")
INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd")
//INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd")
//INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd")
//INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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@ -8,6 +8,22 @@
namespace Dynarmic::A64 {
bool TranslatorVisitor::REV16_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size != 0) {
return UnallocatedEncoding();
}
const size_t datasize = Q ? 128 : 64;
constexpr size_t esize = 16;
const IR::U128 data = V(datasize, Vn);
const IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, 8),
ir.VectorLogicalShiftLeft(esize, data, 8));
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
const auto esize = sz ? 64 : 32;