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A64: Implement FACGT's vector single/double precision variants

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Lioncash 2018-07-06 22:35:33 -04:00 committed by MerryMage
parent fc731dddae
commit 6912a02d9b
2 changed files with 17 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -778,7 +778,7 @@ INST(BSL, "BSL", "0Q101
//INST(FMLSL_vec_2, "FMLSL, FMLSL2 (vector)", "0Q1011101z1mmmmm110011nnnnnddddd")
INST(FABD_4, "FABD", "0Q1011101z1mmmmm110101nnnnnddddd")
INST(FCMGT_reg_4, "FCMGT (register)", "0Q1011101z1mmmmm111001nnnnnddddd")
//INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd")
INST(FACGT_4, "FACGT", "0Q1011101z1mmmmm111011nnnnnddddd")
//INST(FMINP_vec_2, "FMINP (vector)", "0Q1011101z1mmmmm111101nnnnnddddd")
INST(BIT, "BIT", "0Q101110101mmmmm000111nnnnnddddd")
INST(BIF, "BIF", "0Q101110111mmmmm000111nnnnnddddd")

16
src/frontend/A64/translate/impl/simd_three_same.cpp
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@ -380,6 +380,22 @@ bool TranslatorVisitor::FABD_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::FACGT_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();
}
const size_t datasize = Q ? 128 : 64;
const size_t esize = sz ? 64 : 32;
const IR::U128 operand1 = ir.FPVectorAbs(esize, V(datasize, Vn));
const IR::U128 operand2 = ir.FPVectorAbs(esize, V(datasize, Vm));
const IR::U128 result = ir.FPVectorGreater(esize, operand1, operand2);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FADD_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();