A64: Implement USRA (scalar)
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d56fa8f735
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2 changed files with 24 additions and 4 deletions
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@ -478,7 +478,7 @@ INST(SHL_1, "SHL", "01011
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//INST(SCVTF_fix_1, "SCVTF (vector, fixed-point)", "010111110IIIIiii111001nnnnnddddd")
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//INST(FCVTZS_fix_1, "FCVTZS (vector, fixed-point)", "010111110IIIIiii111111nnnnnddddd")
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INST(USHR_1, "USHR", "011111110IIIIiii000001nnnnnddddd")
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//INST(USRA_1, "USRA", "011111110IIIIiii000101nnnnnddddd")
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INST(USRA_1, "USRA", "011111110IIIIiii000101nnnnnddddd")
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//INST(URSHR_1, "URSHR", "011111110IIIIiii001001nnnnnddddd")
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//INST(URSRA_1, "URSRA", "011111110IIIIiii001101nnnnnddddd")
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//INST(SRI_1, "SRI", "011111110IIIIiii010001nnnnnddddd")
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@ -8,18 +8,29 @@
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namespace Dynarmic::A64 {
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static void ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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enum class ShiftExtraBehavior {
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None,
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Accumulate,
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};
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static void ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
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ShiftExtraBehavior behavior) {
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const size_t esize = 64;
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const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
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const IR::U64 operand = v.V_scalar(esize, Vn);
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const IR::U64 result = [&] {
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IR::U64 result = [&] {
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if (shift_amount == esize) {
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return v.ir.Imm64(0);
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}
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return v.ir.LogicalShiftRight(operand, v.ir.Imm8(shift_amount));
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}();
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if (behavior == ShiftExtraBehavior::Accumulate) {
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const IR::U64 addend = v.V_scalar(esize, Vd);
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result = v.ir.Add(result, addend);
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}
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v.V_scalar(esize, Vd, result);
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}
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@ -43,7 +54,16 @@ bool TranslatorVisitor::USHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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return ReservedValue();
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}
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ShiftRight(*this, immh, immb, Vn, Vd);
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ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None);
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return true;
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}
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bool TranslatorVisitor::USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
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if (!immh.Bit<3>()) {
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return ReservedValue();
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}
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ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate);
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return true;
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}
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