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A64: Implement USRA (scalar)

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Lioncash 2018-04-12 14:24:47 -04:00 committed by MerryMage
parent d56fa8f735
commit 6723b00497
2 changed files with 24 additions and 4 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -478,7 +478,7 @@ INST(SHL_1, "SHL", "01011
//INST(SCVTF_fix_1, "SCVTF (vector, fixed-point)", "010111110IIIIiii111001nnnnnddddd") //INST(SCVTF_fix_1, "SCVTF (vector, fixed-point)", "010111110IIIIiii111001nnnnnddddd")
//INST(FCVTZS_fix_1, "FCVTZS (vector, fixed-point)", "010111110IIIIiii111111nnnnnddddd") //INST(FCVTZS_fix_1, "FCVTZS (vector, fixed-point)", "010111110IIIIiii111111nnnnnddddd")
INST(USHR_1, "USHR", "011111110IIIIiii000001nnnnnddddd") INST(USHR_1, "USHR", "011111110IIIIiii000001nnnnnddddd")
//INST(USRA_1, "USRA", "011111110IIIIiii000101nnnnnddddd") INST(USRA_1, "USRA", "011111110IIIIiii000101nnnnnddddd")
//INST(URSHR_1, "URSHR", "011111110IIIIiii001001nnnnnddddd") //INST(URSHR_1, "URSHR", "011111110IIIIiii001001nnnnnddddd")
//INST(URSRA_1, "URSRA", "011111110IIIIiii001101nnnnnddddd") //INST(URSRA_1, "URSRA", "011111110IIIIiii001101nnnnnddddd")
//INST(SRI_1, "SRI", "011111110IIIIiii010001nnnnnddddd") //INST(SRI_1, "SRI", "011111110IIIIiii010001nnnnnddddd")

26
src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
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@ -8,18 +8,29 @@
namespace Dynarmic::A64 { namespace Dynarmic::A64 {
static void ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { enum class ShiftExtraBehavior {
None,
Accumulate,
};
static void ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
ShiftExtraBehavior behavior) {
const size_t esize = 64; const size_t esize = 64;
const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend()); const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
const IR::U64 operand = v.V_scalar(esize, Vn); const IR::U64 operand = v.V_scalar(esize, Vn);
const IR::U64 result = [&] { IR::U64 result = [&] {
if (shift_amount == esize) { if (shift_amount == esize) {
return v.ir.Imm64(0); return v.ir.Imm64(0);
} }
return v.ir.LogicalShiftRight(operand, v.ir.Imm8(shift_amount)); return v.ir.LogicalShiftRight(operand, v.ir.Imm8(shift_amount));
}(); }();
if (behavior == ShiftExtraBehavior::Accumulate) {
const IR::U64 addend = v.V_scalar(esize, Vd);
result = v.ir.Add(result, addend);
}
v.V_scalar(esize, Vd, result); v.V_scalar(esize, Vd, result);
} }
@ -43,7 +54,16 @@ bool TranslatorVisitor::USHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
return ReservedValue(); return ReservedValue();
} }
ShiftRight(*this, immh, immb, Vn, Vd); ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None);
return true;
}
bool TranslatorVisitor::USRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (!immh.Bit<3>()) {
return ReservedValue();
}
ShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate);
return true; return true;
} }