ir: Add opcode for reversing bits in a vector
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4 changed files with 49 additions and 0 deletions
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@ -1276,6 +1276,49 @@ void EmitX64::EmitVectorPopulationCount(EmitContext& ctx, IR::Inst* inst) {
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});
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});
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}
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}
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void EmitX64::EmitVectorReverseBits(EmitContext& ctx, IR::Inst* inst) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm data = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm high_nibble_reg = ctx.reg_alloc.ScratchXmm();
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code.movdqa(high_nibble_reg, code.MConst(xword, 0xF0F0F0F0F0F0F0F0, 0xF0F0F0F0F0F0F0F0));
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code.pand(high_nibble_reg, data);
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code.pxor(data, high_nibble_reg);
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code.psrld(high_nibble_reg, 4);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tSSSE3)) {
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// High lookup
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const Xbyak::Xmm high_reversed_reg = ctx.reg_alloc.ScratchXmm();
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code.movdqa(high_reversed_reg, code.MConst(xword, 0xE060A020C0408000, 0xF070B030D0509010));
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code.pshufb(high_reversed_reg, data);
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// Low lookup (low nibble equivalent of the above)
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code.movdqa(data, code.MConst(xword, 0x0E060A020C040800, 0x0F070B030D050901));
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code.pshufb(data, high_nibble_reg);
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code.por(data, high_reversed_reg);
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} else {
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code.pslld(data, 4);
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code.por(data, high_nibble_reg);
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code.movdqa(high_nibble_reg, code.MConst(xword, 0xCCCCCCCCCCCCCCCC, 0xCCCCCCCCCCCCCCCC));
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code.pand(high_nibble_reg, data);
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code.pxor(data, high_nibble_reg);
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code.psrld(high_nibble_reg, 2);
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code.pslld(data, 2);
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code.por(data, high_nibble_reg);
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code.movdqa(high_nibble_reg, code.MConst(xword, 0xAAAAAAAAAAAAAAAA, 0xAAAAAAAAAAAAAAAA));
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code.pand(high_nibble_reg, data);
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code.pxor(data, high_nibble_reg);
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code.psrld(high_nibble_reg, 1);
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code.paddd(data, data);
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code.por(data, high_nibble_reg);
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}
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ctx.reg_alloc.DefineValue(inst, data);
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}
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enum class ShuffleType {
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enum class ShuffleType {
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LowHalfwords,
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LowHalfwords,
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HighHalfwords,
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HighHalfwords,
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@ -1143,6 +1143,10 @@ U128 IREmitter::VectorPopulationCount(const U128& a) {
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return Inst<U128>(Opcode::VectorPopulationCount, a);
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return Inst<U128>(Opcode::VectorPopulationCount, a);
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}
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}
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U128 IREmitter::VectorReverseBits(const U128& a) {
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return Inst<U128>(Opcode::VectorReverseBits, a);
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}
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U128 IREmitter::VectorShuffleHighHalfwords(const U128& a, u8 mask) {
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U128 IREmitter::VectorShuffleHighHalfwords(const U128& a, u8 mask) {
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return Inst<U128>(Opcode::VectorShuffleHighHalfwords, a, mask);
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return Inst<U128>(Opcode::VectorShuffleHighHalfwords, a, mask);
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}
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}
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@ -242,6 +242,7 @@ public:
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U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);
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U128 VectorPairedAdd(size_t esize, const U128& a, const U128& b);
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U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b);
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U128 VectorPairedAddLower(size_t esize, const U128& a, const U128& b);
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U128 VectorPopulationCount(const U128& a);
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U128 VectorPopulationCount(const U128& a);
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U128 VectorReverseBits(const U128& a);
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U128 VectorShuffleHighHalfwords(const U128& a, u8 mask);
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U128 VectorShuffleHighHalfwords(const U128& a, u8 mask);
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U128 VectorShuffleLowHalfwords(const U128& a, u8 mask);
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U128 VectorShuffleLowHalfwords(const U128& a, u8 mask);
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U128 VectorShuffleWords(const U128& a, u8 mask);
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U128 VectorShuffleWords(const U128& a, u8 mask);
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@ -296,6 +296,7 @@ OPCODE(VectorPairedAdd16, T::U128, T::U128, T::U
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OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
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OPCODE(VectorPairedAdd32, T::U128, T::U128, T::U128 )
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OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
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OPCODE(VectorPairedAdd64, T::U128, T::U128, T::U128 )
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OPCODE(VectorPopulationCount, T::U128, T::U128 )
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OPCODE(VectorPopulationCount, T::U128, T::U128 )
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OPCODE(VectorReverseBits, T::U128, T::U128 )
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OPCODE(VectorShuffleHighHalfwords, T::U128, T::U128, T::U8 )
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OPCODE(VectorShuffleHighHalfwords, T::U128, T::U128, T::U8 )
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OPCODE(VectorShuffleLowHalfwords, T::U128, T::U128, T::U8 )
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OPCODE(VectorShuffleLowHalfwords, T::U128, T::U128, T::U8 )
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OPCODE(VectorShuffleWords, T::U128, T::U128, T::U8 )
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OPCODE(VectorShuffleWords, T::U128, T::U128, T::U8 )
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