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A64: Implement SQSHL's vector immediate variant

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Lioncash 2018-09-16 18:11:11 -04:00 committed by MerryMage
parent e8b0f25dff
commit 616a153c16
2 changed files with 18 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -795,7 +795,7 @@ INST(SSRA_2, "SSRA", "0Q001
INST(SRSHR_2, "SRSHR", "0Q0011110IIIIiii001001nnnnnddddd")
INST(SRSRA_2, "SRSRA", "0Q0011110IIIIiii001101nnnnnddddd")
INST(SHL_2, "SHL", "0Q0011110IIIIiii010101nnnnnddddd")
//INST(SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd")
INST(SQSHL_imm_2, "SQSHL (immediate)", "0Q0011110IIIIiii011101nnnnnddddd")
INST(SHRN, "SHRN, SHRN2", "0Q0011110IIIIiii100001nnnnnddddd")
INST(RSHRN, "RSHRN, RSHRN2", "0Q0011110IIIIiii100011nnnnnddddd")
INST(SQSHRN_2, "SQSHRN, SQSHRN2", "0Q0011110IIIIiii100101nnnnnddddd")

17
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
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@ -198,6 +198,23 @@ bool TranslatorVisitor::RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd)
return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::Truncation, Signedness::Unsigned);
}
bool TranslatorVisitor::SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (!Q && immh.Bit<3>()) {
return ReservedValue();
}
const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend());
const size_t datasize = Q ? 128 : 64;
const size_t shift = concatenate(immh, immb).ZeroExtend() - esize;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 shift_vec = ir.VectorBroadcast(esize, I(esize, shift));
const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand, shift_vec);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToSigned, Signedness::Signed);
}