TranslateArm: Reorganisation - Split visitor into multiple .cpp files
This commit is contained in:
MerryMage
parent
93af160c97
commit
6097a21955
6 changed files with 423 additions and 296 deletions
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@ -16,6 +16,9 @@ set(SRCS
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frontend/ir/ir_emitter.cpp
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frontend/translate/translate.cpp
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frontend/translate/translate_arm.cpp
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frontend/translate/translate_arm/data_processing.cpp
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frontend/translate/translate_arm/exception_generating.cpp
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frontend/translate/translate_arm/reversal.cpp
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frontend/translate/translate_thumb.cpp
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ir_opt/dead_code_elimination_pass.cpp
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ir_opt/get_set_elimination_pass.cpp
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@ -49,6 +52,7 @@ set(HEADERS
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frontend/ir/ir_emitter.h
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frontend/ir/opcodes.h
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frontend/translate/translate.h
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frontend/translate/translate_arm/translate_arm.h
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interface/interface.h
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ir_opt/passes.h
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)
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@ -8,307 +8,12 @@
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#include "frontend/arm_types.h"
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#include "frontend/decoder/arm.h"
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#include "frontend/ir/ir.h"
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#include "frontend/ir/ir_emitter.h"
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#include "frontend/translate/translate.h"
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#include "frontend/translate/translate_arm/translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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namespace {
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enum class ConditionalState {
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/// We haven't met any conditional instructions yet.
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None,
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/// Current instruction is a conditional. This marks the end of this basic block.
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Break,
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/// This basic block is made up solely of conditional instructions.
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Translating,
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};
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struct ArmTranslatorVisitor final {
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explicit ArmTranslatorVisitor(LocationDescriptor descriptor) : ir(descriptor) {
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ASSERT_MSG(!descriptor.TFlag(), "The processor must be in Arm mode");
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}
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IREmitter ir;
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ConditionalState cond_state = ConditionalState::None;
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bool InterpretThisInstruction() {
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ir.SetTerm(IR::Term::Interpret(ir.current_location));
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return false;
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}
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bool UnpredictableInstruction() {
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ASSERT_MSG(false, "UNPREDICTABLE");
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return false;
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}
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bool LinkToNextInstruction() {
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auto next_location = ir.current_location.AdvancePC(4);
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ir.SetTerm(IR::Term::LinkBlock{next_location});
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return false;
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}
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bool ConditionPassed(Cond cond) {
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ASSERT_MSG(cond_state != ConditionalState::Translating,
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"In the current impl, ConditionPassed should never be called again once a non-AL cond is hit. "
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"(i.e.: one and only one conditional instruction per block)");
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ASSERT_MSG(cond_state != ConditionalState::Break,
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"This should never happen. We requested a break but that wasn't honored.");
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ASSERT_MSG(cond != Cond::NV, "NV conditional is obsolete");
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if (cond == Cond::AL) {
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// Everything is fine with the world
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return true;
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}
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// non-AL cond
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if (!ir.block.instructions.empty()) {
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// We've already emitted instructions. Quit for now, we'll make a new block here later.
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cond_state = ConditionalState::Break;
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location});
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return false;
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}
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// We've not emitted instructions yet.
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// We'll emit one instruction, and set the block-entry conditional appropriately.
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cond_state = ConditionalState::Translating;
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ir.block.cond = cond;
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return true;
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}
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static u32 rotr(u32 x, int shift) {
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shift &= 31;
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if (!shift) return x;
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return (x >> shift) | (x << (32 - shift));
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}
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static u32 ArmExpandImm(int rotate, Imm8 imm8) {
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return rotr(static_cast<u32>(imm8), rotate*2);
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}
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bool arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// ADC{S}<c> <Rd>, <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.GetCFlag());
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if (d == Reg::PC) {
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ASSERT(!S);
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ir.ALUWritePC(result.result);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, result.result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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}
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return true;
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};
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bool arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// CMP<c> <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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return true;
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}
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bool arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_SVC(Cond cond, Imm24 imm24) {
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u32 imm32 = imm24;
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// SVC<c> #<imm24>
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if (ConditionPassed(cond)) {
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ir.CallSupervisor(ir.Imm32(imm32));
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return LinkToNextInstruction();
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}
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return true;
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}
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bool arm_UDF() {
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return InterpretThisInstruction();
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}
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bool arm_REV(Cond cond, Reg d, Reg m) {
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// REV<c> <Rd>, <Rm>
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ASSERT(d != Reg::PC && m != Reg::PC);
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if (ConditionPassed(cond)) {
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auto result = ir.ByteReverseWord(ir.GetRegister(m));
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ir.SetRegister(d, result);
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}
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return true;
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}
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bool arm_REV16(Cond cond, Reg d, Reg m) {
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return InterpretThisInstruction();
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}
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bool arm_REVSH(Cond cond, Reg d, Reg m) {
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// REVSH<c> <Rd>, <Rm>
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ASSERT(d != Reg::PC && m != Reg::PC);
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if (ConditionPassed(cond)) {
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auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
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ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
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}
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return true;
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}
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};
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} // local namespace
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IR::Block TranslateArm(LocationDescriptor descriptor, MemoryRead32FuncType memory_read_32) {
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ArmTranslatorVisitor visitor{descriptor};
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@ -342,5 +47,51 @@ IR::Block TranslateArm(LocationDescriptor descriptor, MemoryRead32FuncType memor
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return std::move(visitor.ir.block);
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}
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bool ArmTranslatorVisitor::ConditionPassed(Cond cond) {
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ASSERT_MSG(cond_state != ConditionalState::Translating,
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"In the current impl, ConditionPassed should never be called again once a non-AL cond is hit. "
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"(i.e.: one and only one conditional instruction per block)");
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ASSERT_MSG(cond_state != ConditionalState::Break,
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"This should never happen. We requested a break but that wasn't honored.");
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ASSERT_MSG(cond != Cond::NV, "NV conditional is obsolete");
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if (cond == Cond::AL) {
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// Everything is fine with the world
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return true;
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}
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// non-AL cond
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if (!ir.block.instructions.empty()) {
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// We've already emitted instructions. Quit for now, we'll make a new block here later.
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cond_state = ConditionalState::Break;
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ir.SetTerm(IR::Term::LinkBlock{ir.current_location});
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return false;
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}
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// We've not emitted instructions yet.
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// We'll emit one instruction, and set the block-entry conditional appropriately.
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cond_state = ConditionalState::Translating;
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ir.block.cond = cond;
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return true;
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}
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bool ArmTranslatorVisitor::InterpretThisInstruction() {
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ir.SetTerm(IR::Term::Interpret(ir.current_location));
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return false;
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}
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bool ArmTranslatorVisitor::UnpredictableInstruction() {
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ASSERT_MSG(false, "UNPREDICTABLE");
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return false;
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}
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bool ArmTranslatorVisitor::LinkToNextInstruction() {
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auto next_location = ir.current_location.AdvancePC(4);
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ir.SetTerm(IR::Term::LinkBlock{next_location});
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return false;
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}
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} // namespace Arm
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} // namespace Dynarmic
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191
src/frontend/translate/translate_arm/data_processing.cpp
Normal file
191
src/frontend/translate/translate_arm/data_processing.cpp
Normal file
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@ -0,0 +1,191 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include "translate_arm.h"
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namespace Dynarmic {
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namespace Arm {
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bool ArmTranslatorVisitor::arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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u32 imm32 = ArmExpandImm(rotate, imm8);
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// ADC{S}<c> <Rd>, <Rn>, #<imm>
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if (ConditionPassed(cond)) {
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auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.GetCFlag());
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if (d == Reg::PC) {
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ASSERT(!S);
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ir.ALUWritePC(result.result);
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ir.SetTerm(IR::Term::ReturnToDispatch{});
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return false;
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}
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ir.SetRegister(d, result.result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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}
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}
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return true;
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}
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bool ArmTranslatorVisitor::arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
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return InterpretThisInstruction();
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}
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bool ArmTranslatorVisitor::arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
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return InterpretThisInstruction();
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}
|
||||
bool ArmTranslatorVisitor::arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
u32 imm32 = ArmExpandImm(rotate, imm8);
|
||||
// CMP<c> <Rn>, #<imm>
|
||||
if (ConditionPassed(cond)) {
|
||||
auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
|
||||
ir.SetNFlag(ir.MostSignificantBit(result.result));
|
||||
ir.SetZFlag(ir.IsZero(result.result));
|
||||
ir.SetCFlag(result.carry);
|
||||
ir.SetVFlag(result.overflow);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) {
|
||||
//auto result = ArmExpandImm_C(rotate, imm8);
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
bool ArmTranslatorVisitor::arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
} // namespace Dynarmic
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* This software may be used and distributed according to the terms of the GNU
|
||||
* General Public License version 2 or any later version.
|
||||
*/
|
||||
|
||||
#include "translate_arm.h"
|
||||
|
||||
namespace Dynarmic {
|
||||
namespace Arm {
|
||||
|
||||
bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_SVC(Cond cond, Imm24 imm24) {
|
||||
u32 imm32 = imm24;
|
||||
// SVC<c> #<imm24>
|
||||
if (ConditionPassed(cond)) {
|
||||
ir.CallSupervisor(ir.Imm32(imm32));
|
||||
return LinkToNextInstruction();
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_UDF() {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
} // namespace Dynarmic
|
||||
39
src/frontend/translate/translate_arm/reversal.cpp
Normal file
39
src/frontend/translate/translate_arm/reversal.cpp
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* This software may be used and distributed according to the terms of the GNU
|
||||
* General Public License version 2 or any later version.
|
||||
*/
|
||||
|
||||
#include "translate_arm.h"
|
||||
|
||||
namespace Dynarmic {
|
||||
namespace Arm {
|
||||
|
||||
bool ArmTranslatorVisitor::arm_REV(Cond cond, Reg d, Reg m) {
|
||||
// REV<c> <Rd>, <Rm>
|
||||
ASSERT(d != Reg::PC && m != Reg::PC);
|
||||
|
||||
if (ConditionPassed(cond)) {
|
||||
auto result = ir.ByteReverseWord(ir.GetRegister(m));
|
||||
ir.SetRegister(d, result);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_REV16(Cond cond, Reg d, Reg m) {
|
||||
return InterpretThisInstruction();
|
||||
}
|
||||
|
||||
bool ArmTranslatorVisitor::arm_REVSH(Cond cond, Reg d, Reg m) {
|
||||
// REVSH<c> <Rd>, <Rm>
|
||||
ASSERT(d != Reg::PC && m != Reg::PC);
|
||||
|
||||
if (ConditionPassed(cond)) {
|
||||
auto rev_half = ir.ByteReverseHalf(ir.LeastSignificantHalf(ir.GetRegister(m)));
|
||||
ir.SetRegister(d, ir.SignExtendHalfToWord(rev_half));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
} // namespace Arm
|
||||
} // namespace Dynarmic
|
||||
111
src/frontend/translate/translate_arm/translate_arm.h
Normal file
111
src/frontend/translate/translate_arm/translate_arm.h
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* This file is part of the dynarmic project.
|
||||
* Copyright (c) 2016 MerryMage
|
||||
* This software may be used and distributed according to the terms of the GNU
|
||||
* General Public License version 2 or any later version.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "frontend/ir/ir_emitter.h"
|
||||
|
||||
namespace Dynarmic {
|
||||
namespace Arm {
|
||||
|
||||
enum class ConditionalState {
|
||||
/// We haven't met any conditional instructions yet.
|
||||
None,
|
||||
/// Current instruction is a conditional. This marks the end of this basic block.
|
||||
Break,
|
||||
/// This basic block is made up solely of conditional instructions.
|
||||
Translating,
|
||||
};
|
||||
|
||||
struct ArmTranslatorVisitor final {
|
||||
explicit ArmTranslatorVisitor(LocationDescriptor descriptor) : ir(descriptor) {
|
||||
ASSERT_MSG(!descriptor.TFlag(), "The processor must be in Arm mode");
|
||||
}
|
||||
|
||||
IREmitter ir;
|
||||
ConditionalState cond_state = ConditionalState::None;
|
||||
|
||||
bool ConditionPassed(Cond cond);
|
||||
bool InterpretThisInstruction();
|
||||
bool UnpredictableInstruction();
|
||||
bool LinkToNextInstruction();
|
||||
|
||||
static u32 rotr(u32 x, int shift) {
|
||||
shift &= 31;
|
||||
if (!shift) return x;
|
||||
return (x >> shift) | (x << (32 - shift));
|
||||
}
|
||||
|
||||
static u32 ArmExpandImm(int rotate, Imm8 imm8) {
|
||||
return rotr(static_cast<u32>(imm8), rotate*2);
|
||||
}
|
||||
|
||||
// Data processing instructions
|
||||
bool arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
|
||||
bool arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
|
||||
bool arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8);
|
||||
bool arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
|
||||
bool arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
|
||||
bool arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8);
|
||||
bool arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m);
|
||||
bool arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m);
|
||||
|
||||
// Exception generating instructions
|
||||
bool arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4);
|
||||
bool arm_SVC(Cond cond, Imm24 imm24);
|
||||
bool arm_UDF();
|
||||
|
||||
// Reversal instructions
|
||||
bool arm_REV(Cond cond, Reg d, Reg m);
|
||||
bool arm_REV16(Cond cond, Reg d, Reg m);
|
||||
bool arm_REVSH(Cond cond, Reg d, Reg m);
|
||||
|
||||
// Floating-point three-register data processing instructions
|
||||
bool vfp2_VADD(Cond cond, bool D, bool sz, size_t Vn, size_t Vd, bool N, bool M, size_t Vm);
|
||||
};
|
||||
|
||||
} // namespace Arm
|
||||
} // namespace Dynarmic
|
||||
Loading…
Reference in a new issue