tests/fuzz_thumb: Fuzz instructions that may change the PC
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@ -9,6 +9,7 @@
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#include <catch.hpp>
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#include <common/bit_util.h>
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#include <common/bit_set.h>
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#include "common/common_types.h"
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#include "frontend/disassembler.h"
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@ -87,6 +88,9 @@ static void InterpreterFallback(u32 pc, Dynarmic::Jit* jit) {
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InterpreterClearCache();
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InterpreterMainLoop(&interp_state);
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bool T = Dynarmic::Common::Bit<5>(interp_state.Cpsr);
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interp_state.Reg[15] &= T ? 0xFFFFFFFE : 0xFFFFFFFC;
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jit->Regs() = interp_state.Reg;
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jit->Cpsr() = interp_state.Cpsr;
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}
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@ -188,6 +192,10 @@ void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_e
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interp.NumInstrsToExecute = instructions_to_execute_count;
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InterpreterMainLoop(&interp);
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auto interp_write_records = write_records;
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{
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bool T = Dynarmic::Common::Bit<5>(interp.Cpsr);
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interp.Reg[15] &= T ? 0xFFFFFFFE : 0xFFFFFFFC;
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}
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// Run jit
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write_records.clear();
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@ -272,3 +280,31 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb]") {
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FuzzJitThumb(1024, 1025, 25, instruction_select);
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}
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}
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TEST_CASE("Fuzz Thumb instructions set 2 (affects PC)", "[JitX64][Thumb]") {
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const std::array<InstructionGenerator, 7> instructions = {{
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InstructionGenerator("01000111xmmmm000", // BLX/BX
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[](u16 inst){
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u32 Rm = Dynarmic::Common::Bits<3, 6>(inst);
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return Rm != 15;
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}),
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InstructionGenerator("1010oxxxxxxxxxxx"), // add to pc/sp
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InstructionGenerator("11100xxxxxxxxxxx"), // B
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InstructionGenerator("01000100h0xxxxxx"), // ADD (high registers)
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InstructionGenerator("01000110h0xxxxxx"), // MOV (high registers)
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InstructionGenerator("1101ccccxxxxxxxx", // B<cond>
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[](u16 inst){
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u32 c = Dynarmic::Common::Bits<9, 12>(inst);
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return c < 0b1110; // Don't want SWI or undefined instructions.
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}),
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InstructionGenerator("10110110011x0xxx"), // CPS
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}};
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auto instruction_select = [&]() -> u16 {
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size_t inst_index = RandInt<size_t>(0, instructions.size() - 1);
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return instructions[inst_index].Generate();
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};
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FuzzJitThumb(1, 1, 10000, instruction_select);
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}
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