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emit_arm64_cryptography: Implement most

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Merry 2022-08-06 00:13:10 +01:00 committed by merry
parent a97105c296
commit 600f8e29c1
1 changed files with 51 additions and 28 deletions
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79
src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
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@ -72,34 +72,44 @@ void EmitIR<IR::Opcode::CRC32ISO64>(oaknut::CodeGenerator& code, EmitContext& ct
template<> template<>
void EmitIR<IR::Opcode::AESDecryptSingleRound>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::AESDecryptSingleRound>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qoutput = ctx.reg_alloc.WriteQ(inst);
(void)inst; auto Qinput = ctx.reg_alloc.ReadQ(args[0]);
ASSERT_FALSE("Unimplemented"); RegAlloc::Realize(Qoutput, Qinput);
code.MOVI(Qoutput->toD(), oaknut::RepImm{0});
code.AESD(Qoutput->B16(), Qinput->B16());
} }
template<> template<>
void EmitIR<IR::Opcode::AESEncryptSingleRound>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::AESEncryptSingleRound>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qoutput = ctx.reg_alloc.WriteQ(inst);
(void)inst; auto Qinput = ctx.reg_alloc.ReadQ(args[0]);
ASSERT_FALSE("Unimplemented"); RegAlloc::Realize(Qoutput, Qinput);
code.MOVI(Qoutput->toD(), oaknut::RepImm{0});
code.AESE(Qoutput->B16(), Qinput->B16());
} }
template<> template<>
void EmitIR<IR::Opcode::AESInverseMixColumns>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::AESInverseMixColumns>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qoutput = ctx.reg_alloc.WriteQ(inst);
(void)inst; auto Qinput = ctx.reg_alloc.ReadQ(args[0]);
ASSERT_FALSE("Unimplemented"); RegAlloc::Realize(Qoutput, Qinput);
code.AESIMC(Qoutput->B16(), Qinput->B16());
} }
template<> template<>
void EmitIR<IR::Opcode::AESMixColumns>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::AESMixColumns>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qoutput = ctx.reg_alloc.WriteQ(inst);
(void)inst; auto Qinput = ctx.reg_alloc.ReadQ(args[0]);
ASSERT_FALSE("Unimplemented"); RegAlloc::Realize(Qoutput, Qinput);
code.AESMC(Qoutput->B16(), Qinput->B16());
} }
template<> template<>
@ -112,26 +122,39 @@ void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(oaknut::CodeGenerator& code, E
template<> template<>
void EmitIR<IR::Opcode::SHA256Hash>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::SHA256Hash>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qx = ctx.reg_alloc.ReadWriteQ(args[0], inst);
(void)inst; auto Qy = ctx.reg_alloc.ReadQ(args[1]);
ASSERT_FALSE("Unimplemented"); auto Qz = ctx.reg_alloc.ReadQ(args[2]);
const bool part1 = args[3].GetImmediateU1();
RegAlloc::Realize(Qx, Qy, Qz);
if (part1) {
code.SHA256H(Qx, Qy, Qz->S4());
} else {
code.SHA256H2(Qy, Qx, Qz->S4()); // Yes x and y are swapped
}
} }
template<> template<>
void EmitIR<IR::Opcode::SHA256MessageSchedule0>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::SHA256MessageSchedule0>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qa = ctx.reg_alloc.ReadWriteQ(args[0], inst);
(void)inst; auto Qb = ctx.reg_alloc.ReadQ(args[1]);
ASSERT_FALSE("Unimplemented"); RegAlloc::Realize(Qa, Qb);
code.SHA256SU0(Qa->S4(), Qb->S4());
} }
template<> template<>
void EmitIR<IR::Opcode::SHA256MessageSchedule1>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::SHA256MessageSchedule1>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; auto Qa = ctx.reg_alloc.ReadWriteQ(args[0], inst);
(void)inst; auto Qb = ctx.reg_alloc.ReadQ(args[1]);
ASSERT_FALSE("Unimplemented"); auto Qc = ctx.reg_alloc.ReadQ(args[2]);
RegAlloc::Realize(Qa, Qb, Qc);
code.SHA256SU1(Qa->S4(), Qb->S4(), Qc->S4());
} }
} // namespace Dynarmic::Backend::Arm64 } // namespace Dynarmic::Backend::Arm64