From 5fbfc6c155d35217a56625db9d525eebf809d29d Mon Sep 17 00:00:00 2001 From: MerryMage Date: Thu, 21 Jul 2016 21:48:45 +0100 Subject: [PATCH] Implement some simple IR optimizations (get/set eliminiation and DCE) --- src/CMakeLists.txt | 8 +- src/backend_x64/emit_x64.cpp | 20 +- src/backend_x64/interface_x64.cpp | 4 + src/backend_x64/reg_alloc.cpp | 10 +- src/frontend/arm_types.h | 15 ++ .../disassembler/disassembler_arm.cpp | 202 ++++++------------ .../disassembler/disassembler_thumb.cpp | 202 ++++++------------ src/frontend/ir/ir.cpp | 102 ++++++++- src/frontend/ir/ir.h | 10 +- src/frontend/translate/translate_arm.cpp | 2 +- src/ir_opt/dead_code_elimination_pass.cpp | 37 ++++ src/ir_opt/get_set_elimination_pass.cpp | 108 ++++++++++ src/ir_opt/passes.h | 23 ++ src/ir_opt/verification_pass.cpp | 21 ++ tests/arm/fuzz_arm.cpp | 69 +++++- tests/arm/fuzz_thumb.cpp | 11 +- 16 files changed, 544 insertions(+), 300 deletions(-) create mode 100644 src/ir_opt/dead_code_elimination_pass.cpp create mode 100644 src/ir_opt/get_set_elimination_pass.cpp create mode 100644 src/ir_opt/passes.h create mode 100644 src/ir_opt/verification_pass.cpp diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index d0eb50fa..9e62e98f 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -15,6 +15,11 @@ set(SRCS frontend/ir/ir.cpp frontend/ir/ir_emitter.cpp frontend/translate/translate.cpp + frontend/translate/translate_arm.cpp + frontend/translate/translate_thumb.cpp + ir_opt/dead_code_elimination_pass.cpp + ir_opt/get_set_elimination_pass.cpp + ir_opt/verification_pass.cpp ) set(HEADERS @@ -44,9 +49,8 @@ set(HEADERS frontend/ir/ir_emitter.h frontend/ir/opcodes.h frontend/translate/translate.h - frontend/translate/translate_arm.cpp - frontend/translate/translate_thumb.cpp interface/interface.h + ir_opt/passes.h ) create_directory_groups(${SRCS} ${HEADERS}) diff --git a/src/backend_x64/emit_x64.cpp b/src/backend_x64/emit_x64.cpp index 98db5feb..5de7839c 100644 --- a/src/backend_x64/emit_x64.cpp +++ b/src/backend_x64/emit_x64.cpp @@ -137,7 +137,7 @@ void EmitX64::EmitGetNFlag(IR::Value* value_) { void EmitX64::EmitSetNFlag(IR::Value* value_) { auto value = reinterpret_cast(value_); - X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get()); + X64Reg to_store = reg_alloc.UseScratchRegister(value->GetArg(0).get()); // TODO: Flag optimization @@ -161,7 +161,7 @@ void EmitX64::EmitGetZFlag(IR::Value* value_) { void EmitX64::EmitSetZFlag(IR::Value* value_) { auto value = reinterpret_cast(value_); - X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get()); + X64Reg to_store = reg_alloc.UseScratchRegister(value->GetArg(0).get()); // TODO: Flag optimization @@ -185,7 +185,7 @@ void EmitX64::EmitGetCFlag(IR::Value* value_) { void EmitX64::EmitSetCFlag(IR::Value* value_) { auto value = reinterpret_cast(value_); - X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get()); + X64Reg to_store = reg_alloc.UseScratchRegister(value->GetArg(0).get()); // TODO: Flag optimization @@ -209,7 +209,7 @@ void EmitX64::EmitGetVFlag(IR::Value* value_) { void EmitX64::EmitSetVFlag(IR::Value* value_) { auto value = reinterpret_cast(value_); - X64Reg to_store = reg_alloc.UseRegister(value->GetArg(0).get()); + X64Reg to_store = reg_alloc.UseScratchRegister(value->GetArg(0).get()); // TODO: Flag optimization @@ -221,7 +221,7 @@ void EmitX64::EmitSetVFlag(IR::Value* value_) { void EmitX64::EmitBXWritePC(IR::Value* value_) { auto value = reinterpret_cast(value_); - X64Reg new_pc = reg_alloc.UseRegister(value->GetArg(0).get()); + X64Reg new_pc = reg_alloc.UseScratchRegister(value->GetArg(0).get()); X64Reg tmp1 = reg_alloc.ScratchRegister(); X64Reg tmp2 = reg_alloc.ScratchRegister(); @@ -312,6 +312,7 @@ void EmitX64::EmitLogicalShiftLeft(IR::Value* value_) { X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX}); X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value); X64Reg zero = reg_alloc.ScratchRegister(); + reg_alloc.DecrementRemainingUses(value->GetArg(2).get()); // The 32-bit x64 SHL instruction masks the shift count by 0x1F before performing the shift. // ARM differs from the behaviour: It does not mask the count, so shifts above 31 result in zeros. @@ -363,6 +364,7 @@ void EmitX64::EmitLogicalShiftRight(IR::Value* value_) { X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX}); X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value); X64Reg zero = reg_alloc.ScratchRegister(); + reg_alloc.DecrementRemainingUses(value->GetArg(2).get()); // The 32-bit x64 SHR instruction masks the shift count by 0x1F before performing the shift. // ARM differs from the behaviour: It does not mask the count, so shifts above 31 result in zeros. @@ -414,9 +416,10 @@ void EmitX64::EmitArithmeticShiftRight(IR::Value* value_) { auto carry_inst = FindUseWithOpcode(value, IR::Opcode::GetCarryFromOp); if (!carry_inst) { - X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX}); + X64Reg shift = reg_alloc.UseScratchRegister(value->GetArg(1).get(), {HostLoc::RCX}); X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value); X64Reg const31 = reg_alloc.ScratchRegister(); + reg_alloc.DecrementRemainingUses(value->GetArg(2).get()); // The 32-bit x64 SAR instruction masks the shift count by 0x1F before performing the shift. // ARM differs from the behaviour: It does not mask the count. @@ -425,7 +428,7 @@ void EmitX64::EmitArithmeticShiftRight(IR::Value* value_) { code->MOV(32, R(const31), Imm32(31)); code->MOVZX(32, 8, shift, R(shift)); code->CMP(32, R(shift), Imm32(31)); - code->CMOVcc(32, shift, R(const31), CC_L); + code->CMOVcc(32, shift, R(const31), CC_G); code->SAR(32, R(result), R(shift)); } else { inhibit_emission.insert(carry_inst); @@ -465,13 +468,14 @@ void EmitX64::EmitRotateRight(IR::Value* value_) { if (!carry_inst) { X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX}); X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value); + reg_alloc.DecrementRemainingUses(value->GetArg(2).get()); // x64 ROR instruction does (shift & 0x1F) for us. code->ROR(32, R(result), R(shift)); } else { inhibit_emission.insert(carry_inst); - X64Reg shift = reg_alloc.UseRegister(value->GetArg(1).get(), {HostLoc::RCX}); + X64Reg shift = reg_alloc.UseScratchRegister(value->GetArg(1).get(), {HostLoc::RCX}); X64Reg result = reg_alloc.UseDefRegister(value->GetArg(0).get(), value); X64Reg carry = reg_alloc.UseDefRegister(value->GetArg(2).get(), carry_inst); diff --git a/src/backend_x64/interface_x64.cpp b/src/backend_x64/interface_x64.cpp index 250a3f61..e2616b88 100644 --- a/src/backend_x64/interface_x64.cpp +++ b/src/backend_x64/interface_x64.cpp @@ -16,6 +16,7 @@ #include "frontend/arm_types.h" #include "frontend/translate/translate.h" #include "interface/interface.h" +#include "ir_opt/passes.h" namespace Dynarmic { @@ -53,6 +54,9 @@ private: return code_ptr; IR::Block ir_block = Arm::Translate(descriptor, callbacks.MemoryRead32); + Optimization::GetSetElimination(ir_block); + Optimization::DeadCodeElimination(ir_block); + Optimization::VerificationPass(ir_block); return emitter.Emit(descriptor, ir_block); } }; diff --git a/src/backend_x64/reg_alloc.cpp b/src/backend_x64/reg_alloc.cpp index c6fe7443..a5659099 100644 --- a/src/backend_x64/reg_alloc.cpp +++ b/src/backend_x64/reg_alloc.cpp @@ -141,10 +141,13 @@ Gen::X64Reg RegAlloc::UseScratchRegister(IR::Value* use_value, std::initializer_ if (IsRegisterOccupied(new_location)) { SpillRegister(new_location); + if (current_location != new_location) { + code->MOV(32, Gen::R(hostloc_to_x64.at(new_location)), Gen::R(hostloc_to_x64.at(current_location))); + } + } else { + code->MOV(32, Gen::R(hostloc_to_x64.at(new_location)), Gen::R(hostloc_to_x64.at(current_location))); } - code->MOV(32, Gen::R(hostloc_to_x64.at(new_location)), Gen::R(hostloc_to_x64.at(current_location))); - hostloc_state[new_location] = HostLocState::Scratch; remaining_uses[use_value]--; } else { @@ -203,6 +206,9 @@ void RegAlloc::HostCall(IR::Value* result_def, IR::Value* arg0_use, IR::Value* a ScratchRegister({AbiArgs[i]}); } } + + ScratchRegister({HostLoc::RSP}); + code->MOV(64, Gen::R(Gen::RSP), Gen::MDisp(Gen::R15, offsetof(JitState, save_host_RSP))); } HostLoc RegAlloc::SelectARegister(std::initializer_list desired_locations) const { diff --git a/src/frontend/arm_types.h b/src/frontend/arm_types.h index 3b397553..da0e9330 100644 --- a/src/frontend/arm_types.h +++ b/src/frontend/arm_types.h @@ -6,6 +6,7 @@ #pragma once +#include #include #include #include @@ -19,6 +20,13 @@ enum class Cond { EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV }; +inline const char* CondToString(Cond cond, bool explicit_al = false) { + constexpr std::array cond_strs = { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al" + }; + return (!explicit_al && cond == Cond::AL) ? "" : cond_strs.at(static_cast(cond)); +} + enum class Reg { R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, SP = R13, @@ -36,6 +44,13 @@ inline Reg operator+(Reg reg, int number) { return static_cast(new_reg); } +inline const char* RegToString(Reg reg) { + constexpr std::array reg_strs = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" + }; + return reg_strs.at(static_cast(reg)); +} + using Imm3 = u32; using Imm4 = u32; using Imm5 = u32; diff --git a/src/frontend/disassembler/disassembler_arm.cpp b/src/frontend/disassembler/disassembler_arm.cpp index 67e21207..77985a9a 100644 --- a/src/frontend/disassembler/disassembler_arm.cpp +++ b/src/frontend/disassembler/disassembler_arm.cpp @@ -17,91 +17,11 @@ namespace Arm { class DisassemblerVisitor { public: - const char* CondStr(Cond cond) { - switch (cond) { - case Cond::EQ: - return "eq"; - case Cond::NE: - return "ne"; - case Cond::CS: - return "cs"; - case Cond::CC: - return "cc"; - case Cond::MI: - return "mi"; - case Cond::PL: - return "pl"; - case Cond::VS: - return "vs"; - case Cond::VC: - return "vc"; - case Cond::HI: - return "hi"; - case Cond::LS: - return "ls"; - case Cond::GE: - return "ge"; - case Cond::LT: - return "lt"; - case Cond::GT: - return "gt"; - case Cond::LE: - return "le"; - case Cond::AL: - return ""; - case Cond::NV: - break; - } - assert(false); - return ""; - } - template const char* SignStr(T value) { return value >= 0 ? "+" : "-"; } - const char* RegStr(Reg reg) { - switch (reg) { - case Reg::R0: - return "r0"; - case Reg::R1: - return "r1"; - case Reg::R2: - return "r2"; - case Reg::R3: - return "r3"; - case Reg::R4: - return "r4"; - case Reg::R5: - return "r5"; - case Reg::R6: - return "r6"; - case Reg::R7: - return "r7"; - case Reg::R8: - return "r8"; - case Reg::R9: - return "r9"; - case Reg::R10: - return "r10"; - case Reg::R11: - return "r11"; - case Reg::R12: - return "r12"; - case Reg::R13: - return "sp"; - case Reg::R14: - return "lr"; - case Reg::R15: - return "pc"; - case Reg::INVALID_REG: - break; - } - assert(false); - return ""; - } - u32 rotr(u32 x, int shift) { shift &= 31; if (!shift) return x; @@ -134,13 +54,13 @@ public: std::string RsrStr(Reg s, ShiftType shift, Reg m) { switch (shift){ case ShiftType::LSL: - return Common::StringFromFormat("%s, LSL %s", RegStr(m), RegStr(s)); + return Common::StringFromFormat("%s, LSL %s", RegToString(m), RegToString(s)); case ShiftType::LSR: - return Common::StringFromFormat("%s, LSR %s", RegStr(m), RegStr(s)); + return Common::StringFromFormat("%s, LSR %s", RegToString(m), RegToString(s)); case ShiftType::ASR: - return Common::StringFromFormat("%s, ASR %s", RegStr(m), RegStr(s)); + return Common::StringFromFormat("%s, ASR %s", RegToString(m), RegToString(s)); case ShiftType::ROR: - return Common::StringFromFormat("%s, ROR %s", RegStr(m), RegStr(s)); + return Common::StringFromFormat("%s, ROR %s", RegToString(m), RegToString(s)); } assert(false); return ""; @@ -149,24 +69,24 @@ public: // Branch instructions std::string arm_B(Cond cond, Imm24 imm24) { s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8; - return Common::StringFromFormat("b%s %s#%i", CondStr(cond), SignStr(offset), abs(offset)); + return Common::StringFromFormat("b%s %s#%i", CondToString(cond), SignStr(offset), abs(offset)); } std::string arm_BL(Cond cond, Imm24 imm24) { s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8; - return Common::StringFromFormat("bl%s %s#%i", CondStr(cond), SignStr(offset), abs(offset)); + return Common::StringFromFormat("bl%s %s#%i", CondToString(cond), SignStr(offset), abs(offset)); } std::string arm_BLX_imm(bool H, Imm24 imm24) { s32 offset = Common::SignExtend<26, s32>(imm24 << 2) + 8 + (H ? 2 : 0); return Common::StringFromFormat("blx %s#%i", SignStr(offset), abs(offset)); } std::string arm_BLX_reg(Cond cond, Reg m) { - return Common::StringFromFormat("blx%s %s", CondStr(cond), RegStr(m)); + return Common::StringFromFormat("blx%s %s", CondToString(cond), RegToString(m)); } std::string arm_BX(Cond cond, Reg m) { - return Common::StringFromFormat("bx%s %s", CondStr(cond), RegStr(m)); + return Common::StringFromFormat("bx%s %s", CondToString(cond), RegToString(m)); } std::string arm_BXJ(Cond cond, Reg m) { - return Common::StringFromFormat("bxj%s %s", CondStr(cond), RegStr(m)); + return Common::StringFromFormat("bxj%s %s", CondToString(cond), RegToString(m)); } // Coprocessor instructions @@ -180,154 +100,154 @@ public: // Data processing instructions std::string arm_ADC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("adc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("adc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_ADC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("adc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("adc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_ADC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("adc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("adc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_ADD_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("add%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("add%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_ADD_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("add%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("add%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_ADD_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("add%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("add%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_AND_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("and%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("and%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_AND_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("and%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("and%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_AND_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("and%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("and%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_BIC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("bic%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("bic%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_BIC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("bic%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("bic%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_BIC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("bic%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("bic%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_CMN_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("cmn%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("cmn%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_CMN_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmn%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("cmn%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_CMN_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmn%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("cmn%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_CMP_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("cmp%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("cmp%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_CMP_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmp%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("cmp%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_CMP_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("cmp%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("cmp%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_EOR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("eor%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("eor%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_EOR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("eor%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("eor%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_EOR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("eor%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("eor%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_MOV_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("mov%s%s %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("mov%s%s %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8)); } std::string arm_MOV_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("mov%s%s %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("mov%s%s %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_MOV_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("mov%s%s %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("mov%s%s %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m).c_str()); } std::string arm_MVN_imm(Cond cond, bool S, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("mvn%s%s %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("mvn%s%s %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), ArmExpandImm(rotate, imm8)); } std::string arm_MVN_reg(Cond cond, bool S, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("mvn%s%s %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("mvn%s%s %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_MVN_rsr(Cond cond, bool S, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("mvn%s%s %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("mvn%s%s %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RsrStr(s, shift, m).c_str()); } std::string arm_ORR_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("orr%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("orr%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_ORR_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("orr%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("orr%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_ORR_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("orr%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("orr%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_RSB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("rsb%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("rsb%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_RSB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsb%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("rsb%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_RSB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsb%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("rsb%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_RSC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("rsc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("rsc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_RSC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("rsc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_RSC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("rsc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("rsc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_SBC_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("sbc%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("sbc%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_SBC_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("sbc%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("sbc%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_SBC_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("sbc%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("sbc%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_SUB_imm(Cond cond, bool S, Reg n, Reg d, int rotate, Imm8 imm8) { - return Common::StringFromFormat("sub%s%s %s, %s, #%i", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("sub%s%s %s, %s, #%i", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_SUB_reg(Cond cond, bool S, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("sub%s%s %s, %s, %s%s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("sub%s%s %s, %s, %s%s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_SUB_rsr(Cond cond, bool S, Reg n, Reg d, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("sub%s%s %s, %s, %s", CondStr(cond), S ? "s" : "", RegStr(d), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("sub%s%s %s, %s, %s", CondToString(cond), S ? "s" : "", RegToString(d), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_TEQ_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("teq%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("teq%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_TEQ_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("teq%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("teq%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_TEQ_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("teq%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("teq%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); } std::string arm_TST_imm(Cond cond, Reg n, int rotate, Imm8 imm8) { - return Common::StringFromFormat("tst%s %s, #%i", CondStr(cond), RegStr(n), ArmExpandImm(rotate, imm8)); + return Common::StringFromFormat("tst%s %s, #%i", CondToString(cond), RegToString(n), ArmExpandImm(rotate, imm8)); } std::string arm_TST_reg(Cond cond, Reg n, Imm5 imm5, ShiftType shift, Reg m) { - return Common::StringFromFormat("tst%s %s, %s%s", CondStr(cond), RegStr(n), RegStr(m), ShiftStr(shift, imm5).c_str()); + return Common::StringFromFormat("tst%s %s, %s%s", CondToString(cond), RegToString(n), RegToString(m), ShiftStr(shift, imm5).c_str()); } std::string arm_TST_rsr(Cond cond, Reg n, Reg s, ShiftType shift, Reg m) { - return Common::StringFromFormat("tst%s %s, %s", CondStr(cond), RegStr(n), RsrStr(s, shift, m).c_str()); + return Common::StringFromFormat("tst%s %s, %s", CondToString(cond), RegToString(n), RsrStr(s, shift, m).c_str()); } // Exception generation instructions std::string arm_BKPT(Cond cond, Imm12 imm12, Imm4 imm4) { return "ice"; } std::string arm_SVC(Cond cond, Imm24 imm24) { - return Common::StringFromFormat("svc%s #%u", CondStr(cond), imm24); + return Common::StringFromFormat("svc%s #%u", CondToString(cond), imm24); } std::string arm_UDF() { return Common::StringFromFormat("udf"); @@ -406,13 +326,13 @@ public: // Reversal instructions std::string arm_REV(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("rev%s %s, %s", CondStr(cond), RegStr(d), RegStr(m)); + return Common::StringFromFormat("rev%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); } std::string arm_REV16(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("rev16%s %s, %s", CondStr(cond), RegStr(d), RegStr(m)); + return Common::StringFromFormat("rev16%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); } std::string arm_REVSH(Cond cond, Reg d, Reg m) { - return Common::StringFromFormat("revsh%s %s, %s", CondStr(cond), RegStr(d), RegStr(m)); + return Common::StringFromFormat("revsh%s %s, %s", CondToString(cond), RegToString(d), RegToString(m)); } // Saturation instructions diff --git a/src/frontend/disassembler/disassembler_thumb.cpp b/src/frontend/disassembler/disassembler_thumb.cpp index aa77dd07..49afc573 100644 --- a/src/frontend/disassembler/disassembler_thumb.cpp +++ b/src/frontend/disassembler/disassembler_thumb.cpp @@ -17,91 +17,11 @@ namespace Arm { class DisassemblerVisitor { public: - const char* CondStr(Cond cond) { - switch (cond) { - case Cond::EQ: - return "eq"; - case Cond::NE: - return "ne"; - case Cond::CS: - return "cs"; - case Cond::CC: - return "cc"; - case Cond::MI: - return "mi"; - case Cond::PL: - return "pl"; - case Cond::VS: - return "vs"; - case Cond::VC: - return "vc"; - case Cond::HI: - return "hi"; - case Cond::LS: - return "ls"; - case Cond::GE: - return "ge"; - case Cond::LT: - return "lt"; - case Cond::GT: - return "gt"; - case Cond::LE: - return "le"; - case Cond::AL: - return ""; - case Cond::NV: - break; - } - assert(false); - return ""; - } - template const char* SignStr(T value) { return value >= 0 ? "+" : "-"; } - const char* RegStr(Reg reg) { - switch (reg) { - case Reg::R0: - return "r0"; - case Reg::R1: - return "r1"; - case Reg::R2: - return "r2"; - case Reg::R3: - return "r3"; - case Reg::R4: - return "r4"; - case Reg::R5: - return "r5"; - case Reg::R6: - return "r6"; - case Reg::R7: - return "r7"; - case Reg::R8: - return "r8"; - case Reg::R9: - return "r9"; - case Reg::R10: - return "r10"; - case Reg::R11: - return "r11"; - case Reg::R12: - return "r12"; - case Reg::R13: - return "sp"; - case Reg::R14: - return "lr"; - case Reg::R15: - return "pc"; - case Reg::INVALID_REG: - break; - } - assert(false); - return ""; - } - std::string RegListStr(RegList reg_list) { std::string ret = ""; bool first_reg = true; @@ -109,7 +29,7 @@ public: if (Common::Bit(i, reg_list)) { if (!first_reg) ret += ", "; - ret += RegStr(static_cast(i)); + ret += RegToString(static_cast(i)); first_reg = false; } } @@ -117,210 +37,210 @@ public: } std::string thumb16_LSL_imm(Imm5 imm5, Reg m, Reg d) { - return Common::StringFromFormat("lsls %s, %s, #%u", RegStr(d), RegStr(m), imm5); + return Common::StringFromFormat("lsls %s, %s, #%u", RegToString(d), RegToString(m), imm5); } std::string thumb16_LSR_imm(Imm5 imm5, Reg m, Reg d) { - return Common::StringFromFormat("lsrs %s, %s, #%u", RegStr(d), RegStr(m), imm5); + return Common::StringFromFormat("lsrs %s, %s, #%u", RegToString(d), RegToString(m), imm5); } std::string thumb16_ASR_imm(Imm5 imm5, Reg m, Reg d) { - return Common::StringFromFormat("asrs %s, %s, #%u", RegStr(d), RegStr(m), imm5); + return Common::StringFromFormat("asrs %s, %s, #%u", RegToString(d), RegToString(m), imm5); } std::string thumb16_ADD_reg_t1(Reg m, Reg n, Reg d) { - return Common::StringFromFormat("adds %s, %s, %s", RegStr(d), RegStr(n), RegStr(m)); + return Common::StringFromFormat("adds %s, %s, %s", RegToString(d), RegToString(n), RegToString(m)); } std::string thumb16_SUB_reg(Reg m, Reg n, Reg d) { - return Common::StringFromFormat("subs %s, %s, %s", RegStr(d), RegStr(n), RegStr(m)); + return Common::StringFromFormat("subs %s, %s, %s", RegToString(d), RegToString(n), RegToString(m)); } std::string thumb16_ADD_imm_t1(Imm3 imm3, Reg n, Reg d) { - return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3); + return Common::StringFromFormat("adds %s, %s, #%u", RegToString(d), RegToString(n), imm3); } std::string thumb16_SUB_imm_t1(Imm3 imm3, Reg n, Reg d) { - return Common::StringFromFormat("subs %s, %s, #%u", RegStr(d), RegStr(n), imm3); + return Common::StringFromFormat("subs %s, %s, #%u", RegToString(d), RegToString(n), imm3); } std::string thumb16_MOV_imm(Reg d, Imm8 imm8) { - return Common::StringFromFormat("movs %s, #%u", RegStr(d), imm8); + return Common::StringFromFormat("movs %s, #%u", RegToString(d), imm8); } std::string thumb16_CMP_imm(Reg n, Imm8 imm8) { - return Common::StringFromFormat("cmp %s, #%u", RegStr(n), imm8); + return Common::StringFromFormat("cmp %s, #%u", RegToString(n), imm8); } std::string thumb16_ADD_imm_t2(Reg d_n, Imm8 imm8) { - return Common::StringFromFormat("adds %s, #%u", RegStr(d_n), imm8); + return Common::StringFromFormat("adds %s, #%u", RegToString(d_n), imm8); } std::string thumb16_SUB_imm_t2(Reg d_n, Imm8 imm8) { - return Common::StringFromFormat("subs %s, #%u", RegStr(d_n), imm8); + return Common::StringFromFormat("subs %s, #%u", RegToString(d_n), imm8); } std::string thumb16_AND_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("ands %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_EOR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("eors %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("eors %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_LSL_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("lsls %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("lsls %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_LSR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("lsrs %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("lsrs %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_ASR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("asrs %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("asrs %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_ADC_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("adcs %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("adcs %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_SBC_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("sbcs %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("sbcs %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_ROR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("rors %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("rors %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_TST_reg(Reg m, Reg n) { - return Common::StringFromFormat("tst %s, %s", RegStr(n), RegStr(m)); + return Common::StringFromFormat("tst %s, %s", RegToString(n), RegToString(m)); } std::string thumb16_RSB_imm(Reg n, Reg d) { // Pre-UAL syntax: NEGS , - return Common::StringFromFormat("rsbs %s, %s, #0", RegStr(d), RegStr(n)); + return Common::StringFromFormat("rsbs %s, %s, #0", RegToString(d), RegToString(n)); } std::string thumb16_CMP_reg_t1(Reg m, Reg n) { - return Common::StringFromFormat("cmp %s, %s", RegStr(n), RegStr(m)); + return Common::StringFromFormat("cmp %s, %s", RegToString(n), RegToString(m)); } std::string thumb16_CMN_reg(Reg m, Reg n) { - return Common::StringFromFormat("cmn %s, %s", RegStr(n), RegStr(m)); + return Common::StringFromFormat("cmn %s, %s", RegToString(n), RegToString(m)); } std::string thumb16_ORR_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("orrs %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("orrs %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_BIC_reg(Reg m, Reg d_n) { - return Common::StringFromFormat("bics %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("bics %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_MVN_reg(Reg m, Reg d) { - return Common::StringFromFormat("mvns %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("mvns %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) { Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo; - return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m)); + return Common::StringFromFormat("add %s, %s", RegToString(d_n), RegToString(m)); } std::string thumb16_CMP_reg_t2(bool n_hi, Reg m, Reg n_lo) { Reg n = n_hi ? (n_lo + 8) : n_lo; - return Common::StringFromFormat("cmp %s, %s", RegStr(n), RegStr(m)); + return Common::StringFromFormat("cmp %s, %s", RegToString(n), RegToString(m)); } std::string thumb16_MOV_reg(bool d_hi, Reg m, Reg d_lo) { Reg d = d_hi ? (d_lo + 8) : d_lo; - return Common::StringFromFormat("mov %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("mov %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_LDR_literal(Reg t, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("ldr %s, [pc, #%u]", RegStr(t), imm32); + return Common::StringFromFormat("ldr %s, [pc, #%u]", RegToString(t), imm32); } std::string thumb16_STR_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("str %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("str %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_STRH_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("strh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("strh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_STRB_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("strb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("strb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRSB_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrsb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("ldrsb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDR_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldr %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("ldr %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRH_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("ldrh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRB_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrb %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("ldrb %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_LDRSH_reg(Reg m, Reg n, Reg t) { - return Common::StringFromFormat("ldrsh %s, [%s, %s]", RegStr(t), RegStr(n), RegStr(m)); + return Common::StringFromFormat("ldrsh %s, [%s, %s]", RegToString(t), RegToString(n), RegToString(m)); } std::string thumb16_STR_imm_t1(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("str %s, [%s, #%u]", RegStr(t), RegStr(n), imm32); + return Common::StringFromFormat("str %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); } std::string thumb16_LDR_imm_t1(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("ldr %s, [%s, #%u]", RegStr(t), RegStr(n), imm32); + return Common::StringFromFormat("ldr %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); } std::string thumb16_STRB_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5; - return Common::StringFromFormat("strb %s, [%s, #%u]", RegStr(t), RegStr(n), imm32); + return Common::StringFromFormat("strb %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); } std::string thumb16_LDRB_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5; - return Common::StringFromFormat("ldrb %s, [%s, #%u]", RegStr(t), RegStr(n), imm32); + return Common::StringFromFormat("ldrb %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); } std::string thumb16_STRH_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 1; - return Common::StringFromFormat("strh %s, [%s, #%u]", RegStr(t), RegStr(n), imm32); + return Common::StringFromFormat("strh %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); } std::string thumb16_LDRH_imm(Imm5 imm5, Reg n, Reg t) { u32 imm32 = imm5 << 1; - return Common::StringFromFormat("ldrh %s, [%s, #%u]", RegStr(t), RegStr(n), imm32); + return Common::StringFromFormat("ldrh %s, [%s, #%u]", RegToString(t), RegToString(n), imm32); } std::string thumb16_STR_imm_t2(Reg t, Imm5 imm5) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("str %s, [sp, #%u]", RegStr(t), imm32); + return Common::StringFromFormat("str %s, [sp, #%u]", RegToString(t), imm32); } std::string thumb16_LDR_imm_t2(Reg t, Imm5 imm5) { u32 imm32 = imm5 << 2; - return Common::StringFromFormat("ldr %s, [sp, #%u]", RegStr(t), imm32); + return Common::StringFromFormat("ldr %s, [sp, #%u]", RegToString(t), imm32); } std::string thumb16_ADR(Reg d, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("adr %s, +#%u", RegStr(d), imm32); + return Common::StringFromFormat("adr %s, +#%u", RegToString(d), imm32); } std::string thumb16_ADD_sp_t1(Reg d, Imm8 imm8) { u32 imm32 = imm8 << 2; - return Common::StringFromFormat("add %s, sp, #%u", RegStr(d), imm32); + return Common::StringFromFormat("add %s, sp, #%u", RegToString(d), imm32); } std::string thumb16_ADD_sp_t2(Imm7 imm7) { @@ -334,19 +254,19 @@ public: } std::string thumb16_SXTH(Reg m, Reg d) { - return Common::StringFromFormat("sxth %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("sxth %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_SXTB(Reg m, Reg d) { - return Common::StringFromFormat("sxtb %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("sxtb %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_UXTH(Reg m, Reg d) { - return Common::StringFromFormat("uxth %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("uxth %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_UXTB(Reg m, Reg d) { - return Common::StringFromFormat("uxtb %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("uxtb %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_PUSH(bool M, RegList reg_list) { @@ -364,32 +284,32 @@ public: } std::string thumb16_REV(Reg m, Reg d) { - return Common::StringFromFormat("rev %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("rev %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_REV16(Reg m, Reg d) { - return Common::StringFromFormat("rev16 %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("rev16 %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_REVSH(Reg m, Reg d) { - return Common::StringFromFormat("revsh %s, %s", RegStr(d), RegStr(m)); + return Common::StringFromFormat("revsh %s, %s", RegToString(d), RegToString(m)); } std::string thumb16_STMIA(Reg n, RegList reg_list) { - return Common::StringFromFormat("stm %s!, %s", RegStr(n), RegListStr(reg_list).c_str()); + return Common::StringFromFormat("stm %s!, %s", RegToString(n), RegListStr(reg_list).c_str()); } std::string thumb16_LDMIA(Reg n, RegList reg_list) { bool write_back = !Dynarmic::Common::Bit(static_cast(n), reg_list); - return Common::StringFromFormat("ldm %s%s, %s", RegStr(n), write_back ? "!" : "", RegListStr(reg_list).c_str()); + return Common::StringFromFormat("ldm %s%s, %s", RegToString(n), write_back ? "!" : "", RegListStr(reg_list).c_str()); } std::string thumb16_BX(Reg m) { - return Common::StringFromFormat("bx %s", RegStr(m)); + return Common::StringFromFormat("bx %s", RegToString(m)); } std::string thumb16_BLX_reg(Reg m) { - return Common::StringFromFormat("blx %s", RegStr(m)); + return Common::StringFromFormat("blx %s", RegToString(m)); } std::string thumb16_UDF() { @@ -402,7 +322,7 @@ public: std::string thumb16_B_t1(Cond cond, Imm8 imm8) { s32 imm32 = Common::SignExtend<9, s32>(imm8 << 1) + 4; - return Common::StringFromFormat("b%s %s#%u", CondStr(cond), SignStr(imm32), abs(imm32)); + return Common::StringFromFormat("b%s %s#%u", CondToString(cond), SignStr(imm32), abs(imm32)); } std::string thumb16_B_t2(Imm11 imm11) { diff --git a/src/frontend/ir/ir.cpp b/src/frontend/ir/ir.cpp index c7510395..3bb69132 100644 --- a/src/frontend/ir/ir.cpp +++ b/src/frontend/ir/ir.cpp @@ -8,6 +8,7 @@ #include #include "common/assert.h" +#include "common/string_util.h" #include "frontend/ir/ir.h" namespace Dynarmic { @@ -52,10 +53,10 @@ const char* GetNameOf(Opcode op) { // Value class member definitions void Value::ReplaceUsesWith(ValuePtr replacement) { - for (const auto& use : uses) { + while (!uses.empty()) { + auto use = uses.front(); use.use_owner.lock()->ReplaceUseOfXWithY(use.value.lock(), replacement); } - assert(uses.empty()); } std::vector Value::GetUses() const { @@ -81,6 +82,10 @@ void Value::ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) { ASSERT_MSG(false, "This Value type doesn't use any values. Bug in use management code."); } +void Value::AssertValid() { + ASSERT(std::all_of(uses.begin(), uses.end(), [](const auto& use) { return !use.use_owner.expired(); })); +} + // Inst class member definitions Inst::Inst(Opcode op_) : Value(op_) { @@ -105,8 +110,19 @@ ValuePtr Inst::GetArg(size_t index) const { return args.at(index).lock(); } +void Inst::Invalidate() { + AssertValid(); + ASSERT(!HasUses()); + + auto this_ = shared_from_this(); + for (auto& arg : args) { + arg.lock()->RemoveUse(this_); + } +} + void Inst::AssertValid() { ASSERT(std::all_of(args.begin(), args.end(), [](const auto& arg) { return !arg.expired(); })); + Value::AssertValid(); } void Inst::ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) { @@ -126,5 +142,87 @@ void Inst::ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) { ASSERT_MSG(has_use, "This Inst doesn't have x. Bug in use management code."); } +std::string DumpBlock(const IR::Block& block) { + std::string ret; + + const auto loc_to_string = [](Arm::LocationDescriptor loc) -> std::string { + return Common::StringFromFormat("{%u,%s,%s}", + loc.arm_pc, + loc.TFlag ? "T" : "!T", + loc.EFlag ? "E" : "!E"); + }; + + ret += Common::StringFromFormat("Block: location=%s\n", loc_to_string(block.location).c_str()); + ret += Common::StringFromFormat("cycles=%zu", block.cycle_count); + ret += Common::StringFromFormat(", entry_cond=%s", Arm::CondToString(block.cond, true)); + if (block.cond != Arm::Cond::AL) { + ret += Common::StringFromFormat(", cond_fail=%s", loc_to_string(block.cond_failed.get()).c_str()); + } + ret += "\n"; + + std::map value_to_index; + size_t index = 0; + + const auto arg_to_string = [&value_to_index](IR::ValuePtr arg) -> std::string { + if (!arg) { + return ""; + } + switch (arg->GetOpcode()) { + case Opcode::ImmU1: { + auto inst = reinterpret_cast(arg.get()); + return Common::StringFromFormat("#%s", inst->value ? "1" : "0"); + } + case Opcode::ImmU8: { + auto inst = reinterpret_cast(arg.get()); + return Common::StringFromFormat("#%u", inst->value); + } + case Opcode::ImmU32: { + auto inst = reinterpret_cast(arg.get()); + return Common::StringFromFormat("#%#x", inst->value); + } + case Opcode::ImmRegRef: { + auto inst = reinterpret_cast(arg.get()); + return Arm::RegToString(inst->value); + } + default: { + return Common::StringFromFormat("%%%zu", value_to_index.at(arg.get())); + } + } + }; + + for (const auto& inst_ptr : block.instructions) { + const Opcode op = inst_ptr->GetOpcode(); + switch (op) { + case Opcode::ImmU1: + case Opcode::ImmU8: + case Opcode::ImmU32: + case Opcode::ImmRegRef: + break; + default: { + if (GetTypeOf(op) != Type::Void) { + ret += Common::StringFromFormat("%%%-5zu = ", index); + } else { + ret += " "; // '%00000 = ' -> 1 + 5 + 3 = 9 spaces + } + + ret += GetNameOf(op); + + const size_t arg_count = GetNumArgsOf(op); + const auto inst = reinterpret_cast(inst_ptr.get()); + for (size_t arg_index = 0; arg_index < arg_count; arg_index++) { + ret += arg_index != 0 ? ", " : " "; + ret += arg_to_string(inst->GetArg(arg_index)); + } + + ret += "\n"; + value_to_index[inst_ptr.get()] = index++; + break; + } + } + } + + return ret; +} + } // namespace IR } // namespace Dynarmic diff --git a/src/frontend/ir/ir.h b/src/frontend/ir/ir.h index f7c61229..8e9f8d3f 100644 --- a/src/frontend/ir/ir.h +++ b/src/frontend/ir/ir.h @@ -75,6 +75,11 @@ public: std::vector GetUses() const; + /// Prepare this Value for removal from the instruction stream. + virtual void Invalidate() {} + /// Assert that this Value is valid. + virtual void AssertValid(); + intptr_t GetTag() const { return tag; } void SetTag(intptr_t tag_) { tag = tag_; } @@ -151,7 +156,8 @@ public: /// Get argument number `index`. ValuePtr GetArg(size_t index) const; - void AssertValid(); + void Invalidate() override; + void AssertValid() override; protected: void ReplaceUseOfXWithY(ValuePtr x, ValuePtr y) override; @@ -263,6 +269,8 @@ public: size_t cycle_count = 0; }; +/// Returns a string representation of the contents of block. Intended for debugging. +std::string DumpBlock(const IR::Block& block); } // namespace IR } // namespace Dynarmic diff --git a/src/frontend/translate/translate_arm.cpp b/src/frontend/translate/translate_arm.cpp index 04ffca02..36b709b9 100644 --- a/src/frontend/translate/translate_arm.cpp +++ b/src/frontend/translate/translate_arm.cpp @@ -161,7 +161,7 @@ struct ArmTranslatorVisitor final { u32 imm32 = ArmExpandImm(rotate, imm8); // CMP , # if (ConditionPassed(cond)) { - auto result = ir.AddWithCarry(ir.GetRegister(n), ir.Imm32(~imm32), ir.Imm1(true)); + auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1)); ir.SetNFlag(ir.MostSignificantBit(result.result)); ir.SetZFlag(ir.IsZero(result.result)); ir.SetCFlag(result.carry); diff --git a/src/ir_opt/dead_code_elimination_pass.cpp b/src/ir_opt/dead_code_elimination_pass.cpp new file mode 100644 index 00000000..1fee4b50 --- /dev/null +++ b/src/ir_opt/dead_code_elimination_pass.cpp @@ -0,0 +1,37 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include "common/assert.h" +#include "frontend/ir/ir.h" +#include "ir_opt/passes.h" + +namespace Dynarmic { +namespace Optimization { + +void DeadCodeElimination(IR::Block& block) { + const auto is_side_effect_free = [](IR::Opcode op) -> bool { + return IR::GetTypeOf(op) != IR::Type::Void; + }; + + // We iterate over the instructions in reverse order. + // This is because removing an instruction reduces the number of uses for earlier instructions. + + if (block.instructions.empty()) { + return; + } + + auto iter = block.instructions.end(); + do { + --iter; + if (!(*iter)->HasUses() && is_side_effect_free((*iter)->GetOpcode())) { + (*iter)->Invalidate(); + iter = block.instructions.erase(iter); + } + } while (iter != block.instructions.begin()); +} + +} // namespace Optimization +} // namespace Dynarmic diff --git a/src/ir_opt/get_set_elimination_pass.cpp b/src/ir_opt/get_set_elimination_pass.cpp new file mode 100644 index 00000000..5b573e4a --- /dev/null +++ b/src/ir_opt/get_set_elimination_pass.cpp @@ -0,0 +1,108 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include "common/assert.h" +#include "frontend/ir/ir.h" +#include "ir_opt/passes.h" + +namespace Dynarmic { +namespace Optimization { + +void GetSetElimination(IR::Block& block) { + using Iterator = decltype(block.instructions.begin()); + struct RegisterInfo { + IR::ValuePtr register_value = nullptr; + bool set_instruction_present = false; + Iterator last_set_instruction; + }; + std::array reg_info; + RegisterInfo n_info; + RegisterInfo z_info; + RegisterInfo c_info; + RegisterInfo v_info; + + const auto do_set = [&block](RegisterInfo& info, IR::ValuePtr value, Iterator set_inst) { + if (info.set_instruction_present) { + (*info.last_set_instruction)->Invalidate(); + block.instructions.erase(info.last_set_instruction); + } + + info.register_value = value; + info.set_instruction_present = true; + info.last_set_instruction = set_inst; + }; + + const auto do_get = [](RegisterInfo& info, Iterator get_inst) { + if (!info.register_value) { + info.register_value = *get_inst; + return; + } + (*get_inst)->ReplaceUsesWith(info.register_value); + }; + + for (auto iter = block.instructions.begin(); iter != block.instructions.end(); ++iter) { + switch ((*iter)->GetOpcode()) { + case IR::Opcode::SetRegister: { + auto inst = reinterpret_cast((*iter).get()); + Arm::Reg reg = reinterpret_cast(inst->GetArg(0).get())->value; + if (reg == Arm::Reg::PC) + break; + size_t reg_index = static_cast(reg); + do_set(reg_info[reg_index], inst->GetArg(1), iter); + break; + } + case IR::Opcode::GetRegister: { + auto inst = reinterpret_cast((*iter).get()); + Arm::Reg reg = reinterpret_cast(inst->GetArg(0).get())->value; + ASSERT(reg != Arm::Reg::PC); + size_t reg_index = static_cast(reg); + do_get(reg_info[reg_index], iter); + break; + } + case IR::Opcode::SetNFlag: { + auto inst = reinterpret_cast((*iter).get()); + do_set(n_info, inst->GetArg(0), iter); + break; + } + case IR::Opcode::GetNFlag: { + do_get(n_info, iter); + break; + } + case IR::Opcode::SetZFlag: { + auto inst = reinterpret_cast((*iter).get()); + do_set(z_info, inst->GetArg(0), iter); + break; + } + case IR::Opcode::GetZFlag: { + do_get(z_info, iter); + break; + } + case IR::Opcode::SetCFlag: { + auto inst = reinterpret_cast((*iter).get()); + do_set(c_info, inst->GetArg(0), iter); + break; + } + case IR::Opcode::GetCFlag: { + do_get(c_info, iter); + break; + } + case IR::Opcode::SetVFlag: { + auto inst = reinterpret_cast((*iter).get()); + do_set(v_info, inst->GetArg(0), iter); + break; + } + case IR::Opcode::GetVFlag: { + do_get(v_info, iter); + break; + } + default: + break; + } + } +} + +} // namespace Optimization +} // namespace Dynarmic diff --git a/src/ir_opt/passes.h b/src/ir_opt/passes.h new file mode 100644 index 00000000..8d06509c --- /dev/null +++ b/src/ir_opt/passes.h @@ -0,0 +1,23 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#pragma once + +namespace Dynarmic { +namespace IR { +class Block; +} +} + +namespace Dynarmic { +namespace Optimization { + +void GetSetElimination(IR::Block& block); +void DeadCodeElimination(IR::Block& block); +void VerificationPass(const IR::Block& block); + +} // namespace Optimization +} // namespace Dynarmic diff --git a/src/ir_opt/verification_pass.cpp b/src/ir_opt/verification_pass.cpp new file mode 100644 index 00000000..85fb3799 --- /dev/null +++ b/src/ir_opt/verification_pass.cpp @@ -0,0 +1,21 @@ +/* This file is part of the dynarmic project. + * Copyright (c) 2016 MerryMage + * This software may be used and distributed according to the terms of the GNU + * General Public License version 2 or any later version. + */ + +#include "common/assert.h" +#include "frontend/ir/ir.h" +#include "ir_opt/passes.h" + +namespace Dynarmic { +namespace Optimization { + +void VerificationPass(const IR::Block& block) { + for (const auto& inst : block.instructions) { + inst->AssertValid(); + } +} + +} // namespace Optimization +} // namespace Dynarmic diff --git a/tests/arm/fuzz_arm.cpp b/tests/arm/fuzz_arm.cpp index a520448f..fc5ca0d1 100644 --- a/tests/arm/fuzz_arm.cpp +++ b/tests/arm/fuzz_arm.cpp @@ -9,6 +9,9 @@ #include #include +#include +#include +#include #include "common/bit_util.h" #include "common/common_types.h" @@ -235,6 +238,66 @@ void FuzzJitArm(const size_t instruction_count, const size_t instructions_to_exe } } +TEST_CASE( "arm: Optimization Failure (Randomized test case)", "[arm]" ) { + // This was a randomized test-case that was failing. + // + // IR produced for location {12, !T, !E} was: + // %0 = GetRegister r1 + // %1 = SubWithCarry %0, #0x3e80000, #1 + // %2 = GetCarryFromOp %1 + // %3 = GetOverflowFromOp %1 + // %4 = MostSignificantBit %1 + // SetNFlag %4 + // %6 = IsZero %1 + // SetZFlag %6 + // SetCFlag %2 + // SetVFlag %3 + // %10 = GetRegister r5 + // %11 = AddWithCarry %10, #0x8a00, %2 + // SetRegister r4, %11 + // + // The reference to %2 in instruction %11 was the issue, because instruction %8 + // told the register allocator it was a Use but then modified the value. + // Changing the EmitSet*Flag instruction to declare their arguments as UseScratch + // solved this bug. + + Dynarmic::Jit jit{GetUserCallbacks()}; + code_mem.fill({}); + code_mem[0] = 0xe35f0cd9; // cmp pc, #55552 + code_mem[1] = 0xe11c0474; // tst r12, r4, ror r4 + code_mem[2] = 0xe1a006a7; // mov r0, r7, lsr #13 + code_mem[3] = 0xe35107fa; // cmp r1, #0x3E80000 + code_mem[4] = 0xe2a54c8a; // adc r4, r5, #35328 + code_mem[5] = 0xeafffffe; // b +#0 + + jit.Regs() = { + 0x6973b6bb, 0x267ea626, 0x69debf49, 0x8f976895, 0x4ecd2d0d, 0xcf89b8c7, 0xb6713f85, 0x15e2aa5, + 0xcd14336a, 0xafca0f3e, 0xace2efd9, 0x68fb82cd, 0x775447c0, 0xc9e1f8cd, 0xebe0e626, 0x0 + }; + jit.Cpsr() = 0x000001d0; // User-mode + + jit.Run(6); + + REQUIRE( jit.Regs()[0] == 0x00000af1 ); + REQUIRE( jit.Regs()[1] == 0x267ea626 ); + REQUIRE( jit.Regs()[2] == 0x69debf49 ); + REQUIRE( jit.Regs()[3] == 0x8f976895 ); + REQUIRE( jit.Regs()[4] == 0xcf8a42c8 ); + REQUIRE( jit.Regs()[5] == 0xcf89b8c7 ); + REQUIRE( jit.Regs()[6] == 0xb6713f85 ); + REQUIRE( jit.Regs()[7] == 0x015e2aa5 ); + REQUIRE( jit.Regs()[8] == 0xcd14336a ); + REQUIRE( jit.Regs()[9] == 0xafca0f3e ); + REQUIRE( jit.Regs()[10] == 0xace2efd9 ); + REQUIRE( jit.Regs()[11] == 0x68fb82cd ); + REQUIRE( jit.Regs()[12] == 0x775447c0 ); + REQUIRE( jit.Regs()[13] == 0xc9e1f8cd ); + REQUIRE( jit.Regs()[14] == 0xebe0e626 ); + REQUIRE( jit.Regs()[15] == 0x00000014 ); + REQUIRE( jit.Cpsr() == 0x200001d0 ); +} + + TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") { const std::array imm_instructions = { { @@ -347,6 +410,10 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") { }; }; + SECTION("single instructions") { + FuzzJitArm(1, 2, 10000, instruction_select(/*Rd_can_be_r15=*/false)); + } + SECTION("short blocks") { FuzzJitArm(5, 6, 10000, instruction_select(/*Rd_can_be_r15=*/false)); } @@ -561,4 +628,4 @@ TEST_CASE("Fuzz ARM Load/Store instructions", "[JitX64]") { // TODO FAIL(); } -} \ No newline at end of file +} diff --git a/tests/arm/fuzz_thumb.cpp b/tests/arm/fuzz_thumb.cpp index ba343996..db2292c9 100644 --- a/tests/arm/fuzz_thumb.cpp +++ b/tests/arm/fuzz_thumb.cpp @@ -18,6 +18,9 @@ #include "skyeye_interpreter/dyncom/arm_dyncom_interpreter.h" #include "skyeye_interpreter/skyeye_common/armstate.h" +#include "frontend/translate/translate.h" +#include "ir_opt/passes.h" + struct WriteRecord { size_t size; u32 address; @@ -236,6 +239,12 @@ void FuzzJitThumb(const size_t instruction_count, const size_t instructions_to_e printf("%zu [%x] = %llx\n", record.size, record.address, record.data); } + Dynarmic::IR::Block ir_block = Dynarmic::Arm::Translate({0, true, false}, MemoryRead32); + Dynarmic::Optimization::GetSetElimination(ir_block); + Dynarmic::Optimization::DeadCodeElimination(ir_block); + Dynarmic::Optimization::VerificationPass(ir_block); + printf("\n\nIR:\n%s", Dynarmic::IR::DumpBlock(ir_block).c_str()); + #ifdef _MSC_VER __debugbreak(); #endif @@ -294,7 +303,7 @@ TEST_CASE("Fuzz Thumb instructions set 1", "[JitX64][Thumb]") { } SECTION("long blocks") { - FuzzJitThumb(1024, 1025, 2, instruction_select); + FuzzJitThumb(1024, 1025, 10, instruction_select); } }