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A64: Implement ZIP2

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This commit is contained in:
MerryMage 2018-04-03 10:10:53 +01:00
parent ce5ad240fa
commit 5c95e28ed0
2 changed files with 25 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -519,7 +519,7 @@ INST(SUB_1, "SUB (vector)", "01111
INST(ZIP1, "ZIP1", "0Q001110zz0mmmmm001110nnnnnddddd")
//INST(UZP2, "UZP2", "0Q001110zz0mmmmm010110nnnnnddddd")
//INST(TRN2, "TRN2", "0Q001110zz0mmmmm011010nnnnnddddd")
//INST(ZIP2, "ZIP2", "0Q001110zz0mmmmm011110nnnnnddddd")
INST(ZIP2, "ZIP2", "0Q001110zz0mmmmm011110nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Extract
//INST(EXT, "EXT", "0Q101110000mmmmm0iiii0nnnnnddddd")

24
src/frontend/A64/translate/impl/simd_permute.cpp
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@ -24,4 +24,28 @@ bool TranslatorVisitor::ZIP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::ZIP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend<size_t>();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = V(datasize, Vn);
const IR::U128 operand2 = V(datasize, Vm);
const IR::U128 result = [&]{
if (Q) {
return ir.VectorInterleaveUpper(esize, operand1, operand2);
}
// TODO: Urgh.
const IR::U128 interleaved = ir.VectorInterleaveLower(esize, operand1, operand2);
return ir.VectorZeroUpper(ir.VectorShuffleWords(interleaved, 0b01001110));
}();
V(datasize, Vd, result);
return true;
}
} // namespace Dynarmic::A64