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Remove unreachable code (MSVC warnings)

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This commit is contained in:
MerryMage 2020-04-23 15:44:22 +01:00
parent a8a712c801
commit 5c0bb5cc63
24 changed files with 13 additions and 173 deletions
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1
src/backend/x64/emit_x64.cpp
View file

@ -135,7 +135,6 @@ void EmitX64::EmitGetNZCVFromOp(EmitContext& ctx, IR::Inst* inst) {
return 64;
default:
UNREACHABLE();
return 0;
}
}();

4
src/backend/x64/emit_x64_vector.cpp
View file

@ -3069,7 +3069,6 @@ static void EmitVectorSignedSaturatedAbs(size_t esize, BlockOfCode& code, EmitCo
return code.MConst(xword, 0x8000000000000000, 0x8000000000000000);
default:
UNREACHABLE();
return Xbyak::Address{0};
}
}();
@ -3594,7 +3593,6 @@ static void EmitVectorSignedSaturatedNarrowToSigned(size_t original_esize, Block
break;
default:
UNREACHABLE();
break;
}
const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr().cvt32();
@ -3650,7 +3648,6 @@ static void EmitVectorSignedSaturatedNarrowToUnsigned(size_t original_esize, Blo
break;
default:
UNREACHABLE();
break;
}
const Xbyak::Reg32 bit = ctx.reg_alloc.ScratchGpr().cvt32();
@ -3713,7 +3710,6 @@ static void EmitVectorSignedSaturatedNeg(size_t esize, BlockOfCode& code, EmitCo
return code.MConst(xword, 0x8000000000000000, 0x8000000000000000);
default:
UNREACHABLE();
return Xbyak::Address{0};
}
}();

3
src/backend/x64/emit_x64_vector_floating_point.cpp
View file

@ -237,7 +237,6 @@ struct PairedIndexer {
return std::make_tuple(b[2 * i], b[2 * i + 1]);
}
UNREACHABLE();
return {};
}
};
@ -261,7 +260,6 @@ struct PairedLowerIndexer {
return std::make_tuple(0, 0);
} else {
UNREACHABLE();
return {};
}
}
};
@ -1192,7 +1190,6 @@ void EmitFPVectorRoundInt(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
default:
UNREACHABLE();
}
return 0;
}();
EmitTwoOpVectorOperation<fsize, DefaultIndexer>(code, ctx, inst, [&](const Xbyak::Xmm& result, const Xbyak::Xmm& xmm_a){

3
src/backend/x64/reg_alloc.cpp
View file

@ -41,10 +41,8 @@ static size_t GetBitWidth(IR::Type type) {
case IR::Type::Void:
case IR::Type::Table:
ASSERT_FALSE("Type {} cannot be represented at runtime", type);
return 0;
case IR::Type::Opaque:
ASSERT_FALSE("Not a concrete type");
return 0;
case IR::Type::U1:
return 8;
case IR::Type::U8:
@ -61,7 +59,6 @@ static size_t GetBitWidth(IR::Type type) {
return 32; // TODO: Update to 16 when flags optimization is done
}
UNREACHABLE();
return 0;
}
static bool IsValuelessType(IR::Type type) {

19
src/common/assert.h
View file

@ -24,14 +24,19 @@ template <typename... Ts>
} // namespace Dynarmic::Common
#if defined(__clang) || defined(__GNUC__)
#define UNREACHABLE() __builtin_unreachable()
#define ASSUME(expr) [&]{ if (!(expr)) __builtin_unreachable(); }()
#elif defined(_MSC_VER)
#define UNREACHABLE() __assume(0)
#define ASSUME(expr) __assume(expr)
#if defined(NDEBUG)
#if defined(__clang) || defined(__GNUC__)
#define UNREACHABLE() __builtin_unreachable()
#define ASSUME(expr) [&]{ if (!(expr)) __builtin_unreachable(); }()
#elif defined(_MSC_VER)
#define UNREACHABLE() __assume(0)
#define ASSUME(expr) __assume(expr)
#else
#define UNREACHABLE() ASSERT_FALSE("Unreachable code!")
#define ASSUME(expr)
#endif
#else
#define UNREACHABLE() ASSERT_MSG(false, "Unreachable code!")
#define UNREACHABLE() ASSERT_FALSE("Unreachable code!")
#define ASSUME(expr)
#endif

1
src/common/fp/op/FPRecipEstimate.cpp
View file

@ -52,7 +52,6 @@ FPT FPRecipEstimate(FPT op, FPCR fpcr, FPSR& fpsr) {
default:
UNREACHABLE();
}
return false;
}();
FPProcessException(FPExc::Overflow, fpcr, fpsr);

2
src/frontend/A32/disassembler/disassembler_arm.cpp
View file

@ -181,7 +181,6 @@ public:
CondOrTwo(cond), coproc_no, CRd, n, imm8.ZeroExtend());
}
UNREACHABLE();
return "<internal error>";
}
std::string arm_MCR(Cond cond, size_t opc1, CoprocReg CRn, Reg t, size_t coproc_no, size_t opc2, CoprocReg CRm) {
@ -220,7 +219,6 @@ public:
CondOrTwo(cond), coproc_no, CRd, n, imm8.ZeroExtend());
}
UNREACHABLE();
return "<internal error>";
}
// CRC32 instructions

1
src/frontend/A32/translate/impl/crc32.cpp
View file

@ -75,7 +75,6 @@ bool CRC32Variant(ArmTranslatorVisitor& v, Cond cond, Imm<2> sz, Reg n, Reg d, R
}
UNREACHABLE();
return IR::U32{};
}();
v.ir.SetRegister(d, result);

4
src/frontend/A32/translate/translate_arm.cpp
View file

@ -171,7 +171,6 @@ bool ArmTranslatorVisitor::RaiseException(Exception exception) {
IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitImmShift(IR::U32 value, ShiftType type, Imm<5> imm5, IR::U1 carry_in) {
u8 imm5_value = imm5.ZeroExtend<u8>();
switch (type) {
case ShiftType::LSL:
return ir.LogicalShiftLeft(value, ir.Imm8(imm5_value), carry_in);
@ -188,9 +187,7 @@ IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitImmShift(IR::U32 value, Sh
return ir.RotateRightExtended(value, carry_in);
}
}
UNREACHABLE();
return {};
}
IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitRegShift(IR::U32 value, ShiftType type, IR::U8 amount, IR::U1 carry_in) {
@ -205,7 +202,6 @@ IR::ResultAndCarry<IR::U32> ArmTranslatorVisitor::EmitRegShift(IR::U32 value, Sh
return ir.RotateRight(value, amount, carry_in);
}
UNREACHABLE();
return {};
}
} // namespace Dynarmic::A32

2
src/frontend/A64/translate/impl/floating_point_conversion_fixed_point.cpp
View file

@ -28,7 +28,6 @@ bool TranslatorVisitor::SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
return ir.FPSignedFixedToDouble(intval, fracbits, rounding_mode);
}
UNREACHABLE();
return {};
}();
V_scalar(*fltsize, Vd, fltval);
@ -56,7 +55,6 @@ bool TranslatorVisitor::UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg
return ir.FPUnsignedFixedToDouble(intval, fracbits, rounding_mode);
}
UNREACHABLE();
return {};
}();
V_scalar(*fltsize, Vd, fltval);

1
src/frontend/A64/translate/impl/floating_point_conversion_integer.cpp
View file

@ -76,7 +76,6 @@ bool TranslatorVisitor::FMOV_float_gen(bool sf, Imm<2> type, Imm<1> rmode_0, Imm
return 16;
default:
UNREACHABLE();
return 0;
}
}();

9
src/frontend/A64/translate/impl/impl.cpp
View file

@ -20,7 +20,6 @@ bool TranslatorVisitor::UnpredictableInstruction() {
bool TranslatorVisitor::DecodeError() {
UNREACHABLE();
return false;
}
bool TranslatorVisitor::ReservedValue() {
@ -113,7 +112,6 @@ u64 TranslatorVisitor::AdvSIMDExpandImm(bool op, Imm<4> cmode, Imm<8> imm8) {
}
}
UNREACHABLE();
return 0;
}
IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
@ -167,7 +165,6 @@ IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
return ir.GetSP();
default:
ASSERT_FALSE("SP - get : Invalid bitsize");
return {};
}
}
@ -286,7 +283,6 @@ IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccTyp
return ir.ReadMemory128(address);
default:
ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
return {};
}
}
@ -309,7 +305,6 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType /*acc_
return;
default:
ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
return;
}
}
@ -327,7 +322,6 @@ IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::Ac
return ir.ExclusiveWriteMemory128(address, value);
default:
ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
return {};
}
}
@ -339,7 +333,6 @@ IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
return ir.SignExtendToLong(value);
default:
ASSERT_FALSE("Invalid size parameter {}", to_size);
return {};
}
}
@ -351,7 +344,6 @@ IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
return ir.ZeroExtendToLong(value);
default:
ASSERT_FALSE("Invalid size parameter {}", to_size);
return {};
}
}
@ -368,7 +360,6 @@ IR::U32U64 TranslatorVisitor::ShiftReg(size_t bitsize, Reg reg, Imm<2> shift, IR
return ir.RotateRight(result, amount);
}
UNREACHABLE();
return {};
}
IR::U32U64 TranslatorVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) {

2
src/frontend/A64/translate/impl/simd_across_lanes.cpp
View file

@ -79,7 +79,6 @@ bool FPMinMax(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd, MinMaxOpera
return v.ir.FPMinNumeric(lhs, rhs, true);
default:
UNREACHABLE();
return IR::U32U64{};
}
};
@ -144,7 +143,6 @@ bool ScalarMinMax(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd,
default:
UNREACHABLE();
return IR::U32U64{};
}
};

1
src/frontend/A64/translate/impl/simd_modified_immediate.cpp
View file

@ -72,7 +72,6 @@ bool TranslatorVisitor::MOVI(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<
}
UNREACHABLE();
return true;
}
bool TranslatorVisitor::FMOV_2(bool Q, bool op, Imm<1> a, Imm<1> b, Imm<1> c, Imm<1> d, Imm<1> e, Imm<1> f, Imm<1> g, Imm<1> h, Vec Vd) {

1
src/frontend/A64/translate/impl/simd_scalar_pairwise.cpp
View file

@ -32,7 +32,6 @@ bool FPPairwiseMinMax(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, MinMaxOpera
return v.ir.FPMinNumeric(element1, element2, true);
default:
UNREACHABLE();
return IR::U32U64{};
}
}();

2
src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
View file

@ -201,7 +201,6 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn,
return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
}
UNREACHABLE();
return IR::U128{};
}();
const IR::UAny segment = v.ir.VectorGetElement(esize, result, 0);
@ -252,7 +251,6 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Ve
}
UNREACHABLE();
return {};
}();
v.V_scalar(esize, Vd, result);

1
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -118,7 +118,6 @@ bool ScalarFPCompareRegister(TranslatorVisitor& v, bool sz, Vec Vm, Vec Vn, Vec
}
UNREACHABLE();
return IR::U128{};
}();
v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));

1
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -41,7 +41,6 @@ bool ScalarFPCompareAgainstZero(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd, C
}
UNREACHABLE();
return IR::U128{};
}();
v.V_scalar(datasize, Vd, v.ir.VectorGetElement(esize, result, 0));

2
src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp
View file

@ -129,7 +129,6 @@ bool ShiftRightNarrowing(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb,
return v.ir.VectorSignedSaturatedNarrowToSigned(source_esize, wide_result);
}
UNREACHABLE();
return IR::U128{};
}();
v.Vpart(64, Vd, part, result);
@ -223,7 +222,6 @@ bool ConvertFloat(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn
: v.ir.FPVectorToUnsignedFixed(esize, operand, fbits, rounding_mode);
}
UNREACHABLE();
return IR::U128{};
}();
v.V(datasize, Vd, result);

3
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -160,7 +160,6 @@ bool FPCompareRegister(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve
}
UNREACHABLE();
return IR::U128{};
}();
v.V(datasize, Vd, result);
@ -199,7 +198,6 @@ bool VectorMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Ve
default:
UNREACHABLE();
return IR::U128{};
}
}();
@ -282,7 +280,6 @@ bool PairedMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Ve
default:
UNREACHABLE();
return IR::U128{};
}
}();

1
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -75,7 +75,6 @@ bool FPCompareAgainstZero(TranslatorVisitor& v, bool Q, bool sz, Vec Vn, Vec Vd,
}
UNREACHABLE();
return IR::U128{};
}();
v.V(datasize, Vd, result);

2
src/frontend/A64/translate/impl/simd_vector_x_indexed_element.cpp
View file

@ -82,7 +82,6 @@ bool FPMultiplyByElement(TranslatorVisitor& v, bool Q, bool sz, Imm<1> L, Imm<1>
return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
}
UNREACHABLE();
return IR::U128{};
}();
v.V(datasize, Vd, result);
return true;
@ -115,7 +114,6 @@ bool FPMultiplyByElementHalfPrecision(TranslatorVisitor& v, bool Q, Imm<1> L, Im
return v.ir.FPVectorMulAdd(esize, operand3, v.ir.FPVectorNeg(esize, operand1), operand2);
}
UNREACHABLE();
return IR::U128{};
}();
v.V(datasize, Vd, result);
return true;

117
src/frontend/ir/ir_emitter.cpp
View file

@ -350,7 +350,6 @@ U64 IREmitter::SignExtendToLong(const UAny& a) {
return U64(a);
default:
UNREACHABLE();
return {};
}
}
@ -366,7 +365,6 @@ U32 IREmitter::SignExtendToWord(const UAny& a) {
return Inst<U32>(Opcode::LeastSignificantWord, a);
default:
UNREACHABLE();
return {};
}
}
@ -394,7 +392,6 @@ U64 IREmitter::ZeroExtendToLong(const UAny& a) {
return U64(a);
default:
UNREACHABLE();
return {};
}
}
@ -410,7 +407,6 @@ U32 IREmitter::ZeroExtendToWord(const UAny& a) {
return Inst<U32>(Opcode::LeastSignificantWord, a);
default:
UNREACHABLE();
return {};
}
}
@ -540,7 +536,6 @@ ResultAndOverflow<UAny> IREmitter::SignedSaturatedDoublingMultiplyReturnHigh(con
return Inst<U32>(Opcode::SignedSaturatedDoublingMultiplyReturnHigh32, a, b);
default:
UNREACHABLE();
return IR::UAny{};
}
}();
@ -847,7 +842,6 @@ UAny IREmitter::VectorGetElement(size_t esize, const U128& a, size_t index) {
return Inst<U64>(Opcode::VectorGetElement64, a, Imm8(static_cast<u8>(index)));
default:
UNREACHABLE();
return {};
}
}
@ -864,7 +858,6 @@ U128 IREmitter::VectorSetElement(size_t esize, const U128& a, size_t index, cons
return Inst<U128>(Opcode::VectorSetElement64, a, Imm8(static_cast<u8>(index)), elem);
default:
UNREACHABLE();
return {};
}
}
@ -880,7 +873,6 @@ U128 IREmitter::VectorAbs(size_t esize, const U128& a) {
return Inst<U128>(Opcode::VectorAbs64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorAdd(size_t esize, const U128& a, const U128& b) {
@ -895,7 +887,6 @@ U128 IREmitter::VectorAdd(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorAdd64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorAnd(const U128& a, const U128& b) {
@ -914,7 +905,6 @@ U128 IREmitter::VectorArithmeticShiftRight(size_t esize, const U128& a, u8 shift
return Inst<U128>(Opcode::VectorArithmeticShiftRight64, a, Imm8(shift_amount));
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorArithmeticVShift(size_t esize, const U128& a, const U128& b) {
@ -929,7 +919,6 @@ U128 IREmitter::VectorArithmeticVShift(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::VectorArithmeticVShift64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorBroadcastLower(size_t esize, const UAny& a) {
@ -942,7 +931,6 @@ U128 IREmitter::VectorBroadcastLower(size_t esize, const UAny& a) {
return Inst<U128>(Opcode::VectorBroadcastLower32, U32(a));
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorBroadcast(size_t esize, const UAny& a) {
@ -957,7 +945,6 @@ U128 IREmitter::VectorBroadcast(size_t esize, const UAny& a) {
return Inst<U128>(Opcode::VectorBroadcast64, U64(a));
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorCountLeadingZeros(size_t esize, const U128& a) {
@ -970,7 +957,6 @@ U128 IREmitter::VectorCountLeadingZeros(size_t esize, const U128& a) {
return Inst<U128>(Opcode::VectorCountLeadingZeros32, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorDeinterleaveEven(size_t esize, const U128& a, const U128& b) {
@ -985,7 +971,6 @@ U128 IREmitter::VectorDeinterleaveEven(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::VectorDeinterleaveEven64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b) {
@ -1000,7 +985,6 @@ U128 IREmitter::VectorDeinterleaveOdd(size_t esize, const U128& a, const U128& b
return Inst<U128>(Opcode::VectorDeinterleaveOdd64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorEor(const U128& a, const U128& b) {
@ -1021,7 +1005,6 @@ U128 IREmitter::VectorEqual(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorEqual128, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorExtract(const U128& a, const U128& b, size_t position) {
@ -1046,7 +1029,6 @@ U128 IREmitter::VectorGreaterSigned(size_t esize, const U128& a, const U128& b)
return Inst<U128>(Opcode::VectorGreaterS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorGreaterEqualSigned(size_t esize, const U128& a, const U128& b) {
@ -1071,7 +1053,6 @@ U128 IREmitter::VectorHalvingAddSigned(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::VectorHalvingAddS32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1084,7 +1065,6 @@ U128 IREmitter::VectorHalvingAddUnsigned(size_t esize, const U128& a, const U128
return Inst<U128>(Opcode::VectorHalvingAddU32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorHalvingSubSigned(size_t esize, const U128& a, const U128& b) {
@ -1097,7 +1077,6 @@ U128 IREmitter::VectorHalvingSubSigned(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::VectorHalvingSubS32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1110,7 +1089,6 @@ U128 IREmitter::VectorHalvingSubUnsigned(size_t esize, const U128& a, const U128
return Inst<U128>(Opcode::VectorHalvingSubU32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorInterleaveLower(size_t esize, const U128& a, const U128& b) {
@ -1125,7 +1103,6 @@ U128 IREmitter::VectorInterleaveLower(size_t esize, const U128& a, const U128& b
return Inst<U128>(Opcode::VectorInterleaveLower64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorInterleaveUpper(size_t esize, const U128& a, const U128& b) {
@ -1140,7 +1117,6 @@ U128 IREmitter::VectorInterleaveUpper(size_t esize, const U128& a, const U128& b
return Inst<U128>(Opcode::VectorInterleaveUpper64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorLessEqualSigned(size_t esize, const U128& a, const U128& b) {
@ -1171,7 +1147,6 @@ U128 IREmitter::VectorLogicalShiftLeft(size_t esize, const U128& a, u8 shift_amo
return Inst<U128>(Opcode::VectorLogicalShiftLeft64, a, Imm8(shift_amount));
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_amount) {
@ -1186,7 +1161,6 @@ U128 IREmitter::VectorLogicalShiftRight(size_t esize, const U128& a, u8 shift_am
return Inst<U128>(Opcode::VectorLogicalShiftRight64, a, Imm8(shift_amount));
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorLogicalVShift(size_t esize, const U128& a, const U128& b) {
@ -1201,7 +1175,6 @@ U128 IREmitter::VectorLogicalVShift(size_t esize, const U128& a, const U128& b)
return Inst<U128>(Opcode::VectorLogicalVShift64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorMaxSigned(size_t esize, const U128& a, const U128& b) {
@ -1216,7 +1189,6 @@ U128 IREmitter::VectorMaxSigned(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorMaxS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorMaxUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1231,7 +1203,6 @@ U128 IREmitter::VectorMaxUnsigned(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorMaxU64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorMinSigned(size_t esize, const U128& a, const U128& b) {
@ -1246,7 +1217,6 @@ U128 IREmitter::VectorMinSigned(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorMinS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorMinUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1261,7 +1231,6 @@ U128 IREmitter::VectorMinUnsigned(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorMinU64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorMultiply(size_t esize, const U128& a, const U128& b) {
@ -1276,7 +1245,6 @@ U128 IREmitter::VectorMultiply(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorMultiply64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorNarrow(size_t original_esize, const U128& a) {
@ -1289,7 +1257,6 @@ U128 IREmitter::VectorNarrow(size_t original_esize, const U128& a) {
return Inst<U128>(Opcode::VectorNarrow64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorNot(const U128& a) {
@ -1312,7 +1279,6 @@ U128 IREmitter::VectorPairedAdd(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorPairedAdd64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorPairedAddLower(size_t esize, const U128& a, const U128& b) {
@ -1325,7 +1291,6 @@ U128 IREmitter::VectorPairedAddLower(size_t esize, const U128& a, const U128& b)
return Inst<U128>(Opcode::VectorPairedAddLower32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorPairedAddSignedWiden(size_t original_esize, const U128& a) {
@ -1338,7 +1303,6 @@ U128 IREmitter::VectorPairedAddSignedWiden(size_t original_esize, const U128& a)
return Inst<U128>(Opcode::VectorPairedAddSignedWiden32, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorPairedAddUnsignedWiden(size_t original_esize, const U128& a) {
@ -1351,7 +1315,6 @@ U128 IREmitter::VectorPairedAddUnsignedWiden(size_t original_esize, const U128&
return Inst<U128>(Opcode::VectorPairedAddUnsignedWiden32, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b) {
@ -1364,7 +1327,6 @@ U128 IREmitter::VectorPairedMaxSigned(size_t esize, const U128& a, const U128& b
return Inst<U128>(Opcode::VectorPairedMaxS32, a, b);
default:
UNREACHABLE();
return {};
}
}
@ -1378,7 +1340,6 @@ U128 IREmitter::VectorPairedMaxUnsigned(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::VectorPairedMaxU32, a, b);
default:
UNREACHABLE();
return {};
}
}
@ -1392,7 +1353,6 @@ U128 IREmitter::VectorPairedMinSigned(size_t esize, const U128& a, const U128& b
return Inst<U128>(Opcode::VectorPairedMinS32, a, b);
default:
UNREACHABLE();
return {};
}
}
@ -1406,7 +1366,6 @@ U128 IREmitter::VectorPairedMinUnsigned(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::VectorPairedMinU32, a, b);
default:
UNREACHABLE();
return {};
}
}
@ -1422,7 +1381,6 @@ U128 IREmitter::VectorPolynomialMultiplyLong(size_t esize, const U128& a, const
return Inst<U128>(Opcode::VectorPolynomialMultiplyLong64, a, b);
default:
UNREACHABLE();
return {};
}
}
@ -1467,7 +1425,6 @@ U128 IREmitter::VectorRoundingHalvingAddSigned(size_t esize, const U128& a, cons
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1481,7 +1438,6 @@ U128 IREmitter::VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, co
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) {
@ -1497,7 +1453,6 @@ U128 IREmitter::VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1513,7 +1468,6 @@ U128 IREmitter::VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, con
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorShuffleHighHalfwords(const U128& a, u8 mask) {
@ -1540,7 +1494,6 @@ U128 IREmitter::VectorSignExtend(size_t original_esize, const U128& a) {
return Inst<U128>(Opcode::VectorSignExtend64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedAbsoluteDifference(size_t esize, const U128& a, const U128& b) {
@ -1553,7 +1506,6 @@ U128 IREmitter::VectorSignedAbsoluteDifference(size_t esize, const U128& a, cons
return Inst<U128>(Opcode::VectorSignedAbsoluteDifference32, a, b);
}
UNREACHABLE();
return {};
}
UpperAndLower IREmitter::VectorSignedMultiply(size_t esize, const U128& a, const U128& b) {
@ -1565,7 +1517,6 @@ UpperAndLower IREmitter::VectorSignedMultiply(size_t esize, const U128& a, const
return Inst(Opcode::VectorSignedMultiply32, a, b);
}
UNREACHABLE();
return Value{};
}();
return {
@ -1586,7 +1537,6 @@ U128 IREmitter::VectorSignedSaturatedAbs(size_t esize, const U128& a) {
return Inst<U128>(Opcode::VectorSignedSaturatedAbs64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1601,7 +1551,6 @@ U128 IREmitter::VectorSignedSaturatedAccumulateUnsigned(size_t esize, const U128
return Inst<U128>(Opcode::VectorSignedSaturatedAccumulateUnsigned64, a, b);
}
UNREACHABLE();
return {};
}
UpperAndLower IREmitter::VectorSignedSaturatedDoublingMultiply(size_t esize, const U128& a, const U128& b) {
@ -1613,7 +1562,6 @@ UpperAndLower IREmitter::VectorSignedSaturatedDoublingMultiply(size_t esize, con
return Inst(Opcode::VectorSignedSaturatedDoublingMultiply32, a, b);
default:
UNREACHABLE();
return Value{};
}
}();
@ -1631,7 +1579,6 @@ U128 IREmitter::VectorSignedSaturatedDoublingMultiplyLong(size_t esize, const U1
return Inst<U128>(Opcode::VectorSignedSaturatedDoublingMultiplyLong32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedSaturatedNarrowToSigned(size_t original_esize, const U128& a) {
@ -1644,7 +1591,6 @@ U128 IREmitter::VectorSignedSaturatedNarrowToSigned(size_t original_esize, const
return Inst<U128>(Opcode::VectorSignedSaturatedNarrowToSigned64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, const U128& a) {
@ -1657,7 +1603,6 @@ U128 IREmitter::VectorSignedSaturatedNarrowToUnsigned(size_t original_esize, con
return Inst<U128>(Opcode::VectorSignedSaturatedNarrowToUnsigned64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedSaturatedNeg(size_t esize, const U128& a) {
@ -1672,7 +1617,6 @@ U128 IREmitter::VectorSignedSaturatedNeg(size_t esize, const U128& a) {
return Inst<U128>(Opcode::VectorSignedSaturatedNeg64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) {
@ -1687,7 +1631,6 @@ U128 IREmitter::VectorSignedSaturatedShiftLeft(size_t esize, const U128& a, cons
return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeft64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) {
@ -1702,7 +1645,6 @@ U128 IREmitter::VectorSignedSaturatedShiftLeftUnsigned(size_t esize, const U128&
return Inst<U128>(Opcode::VectorSignedSaturatedShiftLeftUnsigned64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorSub(size_t esize, const U128& a, const U128& b) {
@ -1717,7 +1659,6 @@ U128 IREmitter::VectorSub(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::VectorSub64, a, b);
}
UNREACHABLE();
return {};
}
Table IREmitter::VectorTable(std::vector<U128> values) {
@ -1740,7 +1681,6 @@ U128 IREmitter::VectorUnsignedAbsoluteDifference(size_t esize, const U128& a, co
return Inst<U128>(Opcode::VectorUnsignedAbsoluteDifference32, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorUnsignedRecipEstimate(const U128& a) {
@ -1763,7 +1703,6 @@ U128 IREmitter::VectorUnsignedSaturatedAccumulateSigned(size_t esize, const U128
return Inst<U128>(Opcode::VectorUnsignedSaturatedAccumulateSigned64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorUnsignedSaturatedNarrow(size_t esize, const U128& a) {
@ -1776,7 +1715,6 @@ U128 IREmitter::VectorUnsignedSaturatedNarrow(size_t esize, const U128& a) {
return Inst<U128>(Opcode::VectorUnsignedSaturatedNarrow64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, const U128& b) {
@ -1791,7 +1729,6 @@ U128 IREmitter::VectorUnsignedSaturatedShiftLeft(size_t esize, const U128& a, co
return Inst<U128>(Opcode::VectorUnsignedSaturatedShiftLeft64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorZeroExtend(size_t original_esize, const U128& a) {
@ -1806,7 +1743,6 @@ U128 IREmitter::VectorZeroExtend(size_t original_esize, const U128& a) {
return Inst<U128>(Opcode::VectorZeroExtend64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorZeroUpper(const U128& a) {
@ -1827,7 +1763,6 @@ U16U32U64 IREmitter::FPAbs(const U16U32U64& a) {
return Inst<U64>(Opcode::FPAbs64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -1842,7 +1777,6 @@ U32U64 IREmitter::FPAdd(const U32U64& a, const U32U64& b, bool fpcr_controlled)
return Inst<U64>(Opcode::FPAdd64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1859,7 +1793,6 @@ NZCV IREmitter::FPCompare(const U32U64& a, const U32U64& b, bool exc_on_qnan, bo
return Inst<NZCV>(Opcode::FPCompare64, a, b, exc_on_qnan_imm);
default:
UNREACHABLE();
return NZCV{};
}
}
@ -1874,7 +1807,6 @@ U32U64 IREmitter::FPDiv(const U32U64& a, const U32U64& b, bool fpcr_controlled)
return Inst<U64>(Opcode::FPDiv64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1889,7 +1821,6 @@ U32U64 IREmitter::FPMax(const U32U64& a, const U32U64& b, bool fpcr_controlled)
return Inst<U64>(Opcode::FPMax64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1904,7 +1835,6 @@ U32U64 IREmitter::FPMaxNumeric(const U32U64& a, const U32U64& b, bool fpcr_contr
return Inst<U64>(Opcode::FPMaxNumeric64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1919,7 +1849,6 @@ U32U64 IREmitter::FPMin(const U32U64& a, const U32U64& b, bool fpcr_controlled)
return Inst<U64>(Opcode::FPMin64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1934,7 +1863,6 @@ U32U64 IREmitter::FPMinNumeric(const U32U64& a, const U32U64& b, bool fpcr_contr
return Inst<U64>(Opcode::FPMinNumeric64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1949,7 +1877,6 @@ U32U64 IREmitter::FPMul(const U32U64& a, const U32U64& b, bool fpcr_controlled)
return Inst<U64>(Opcode::FPMul64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1966,7 +1893,6 @@ U16U32U64 IREmitter::FPMulAdd(const U16U32U64& a, const U16U32U64& b, const U16U
return Inst<U64>(Opcode::FPMulAdd64, a, b, c);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -1980,7 +1906,6 @@ U32U64 IREmitter::FPMulX(const U32U64& a, const U32U64& b) {
return Inst<U64>(Opcode::FPMulX64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -1994,7 +1919,6 @@ U16U32U64 IREmitter::FPNeg(const U16U32U64& a) {
return Inst<U64>(Opcode::FPNeg64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2008,7 +1932,6 @@ U16U32U64 IREmitter::FPRecipEstimate(const U16U32U64& a) {
return Inst<U64>(Opcode::FPRecipEstimate64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2022,7 +1945,6 @@ U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) {
return Inst<U64>(Opcode::FPRecipExponent64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2038,7 +1960,6 @@ U16U32U64 IREmitter::FPRecipStepFused(const U16U32U64& a, const U16U32U64& b) {
return Inst<U64>(Opcode::FPRecipStepFused64, a, b);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2055,7 +1976,6 @@ U16U32U64 IREmitter::FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, b
return Inst<U64>(Opcode::FPRoundInt64, a, rounding_value, exact_imm);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2069,7 +1989,6 @@ U16U32U64 IREmitter::FPRSqrtEstimate(const U16U32U64& a) {
return Inst<U64>(Opcode::FPRSqrtEstimate64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2085,7 +2004,6 @@ U16U32U64 IREmitter::FPRSqrtStepFused(const U16U32U64& a, const U16U32U64& b) {
return Inst<U64>(Opcode::FPRSqrtStepFused64, a, b);
default:
UNREACHABLE();
return U16U32U64{};
}
}
@ -2097,7 +2015,6 @@ U32U64 IREmitter::FPSqrt(const U32U64& a) {
return Inst<U64>(Opcode::FPSqrt64, a);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -2112,7 +2029,6 @@ U32U64 IREmitter::FPSub(const U32U64& a, const U32U64& b, bool fpcr_controlled)
return Inst<U64>(Opcode::FPSub64, a, b);
default:
UNREACHABLE();
return U32U64{};
}
}
@ -2155,7 +2071,6 @@ U32 IREmitter::FPToFixedS32(const U16U32U64& a, size_t fbits, FP::RoundingMode r
return Inst<U32>(Opcode::FPDoubleToFixedS32, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U32{};
}
}
@ -2174,7 +2089,6 @@ U64 IREmitter::FPToFixedS64(const U16U32U64& a, size_t fbits, FP::RoundingMode r
return Inst<U64>(Opcode::FPDoubleToFixedS64, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U64{};
}
}
@ -2193,7 +2107,6 @@ U32 IREmitter::FPToFixedU32(const U16U32U64& a, size_t fbits, FP::RoundingMode r
return Inst<U32>(Opcode::FPDoubleToFixedU32, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U32{};
}
}
@ -2212,7 +2125,6 @@ U64 IREmitter::FPToFixedU64(const U16U32U64& a, size_t fbits, FP::RoundingMode r
return Inst<U64>(Opcode::FPDoubleToFixedU64, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U64{};
}
}
@ -2229,7 +2141,6 @@ U32 IREmitter::FPSignedFixedToSingle(const U32U64& a, size_t fbits, FP::Rounding
return Inst<U32>(Opcode::FPFixedS64ToSingle, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U32{};
}
}
@ -2246,7 +2157,6 @@ U32 IREmitter::FPUnsignedFixedToSingle(const U32U64& a, size_t fbits, FP::Roundi
return Inst<U32>(Opcode::FPFixedU64ToSingle, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U32{};
}
}
@ -2263,7 +2173,6 @@ U64 IREmitter::FPSignedFixedToDouble(const U32U64& a, size_t fbits, FP::Rounding
return Inst<U64>(Opcode::FPFixedS64ToDouble, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U64{};
}
}
@ -2280,7 +2189,6 @@ U64 IREmitter::FPUnsignedFixedToDouble(const U32U64& a, size_t fbits, FP::Roundi
return Inst<U64>(Opcode::FPFixedU64ToDouble, a, fbits_imm, rounding_imm);
default:
UNREACHABLE();
return U64{};
}
}
@ -2294,7 +2202,6 @@ U128 IREmitter::FPVectorAbs(size_t esize, const U128& a) {
return Inst<U128>(Opcode::FPVectorAbs64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorAdd(size_t esize, const U128& a, const U128& b) {
@ -2305,7 +2212,6 @@ U128 IREmitter::FPVectorAdd(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorAdd64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorDiv(size_t esize, const U128& a, const U128& b) {
@ -2316,7 +2222,6 @@ U128 IREmitter::FPVectorDiv(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorDiv64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) {
@ -2329,7 +2234,6 @@ U128 IREmitter::FPVectorEqual(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorEqual64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
@ -2341,7 +2245,6 @@ U128 IREmitter::FPVectorFromSignedFixed(size_t esize, const U128& a, size_t fbit
return Inst<U128>(Opcode::FPVectorFromSignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
@ -2353,7 +2256,6 @@ U128 IREmitter::FPVectorFromUnsignedFixed(size_t esize, const U128& a, size_t fb
return Inst<U128>(Opcode::FPVectorFromUnsignedFixed64, a, Imm8(static_cast<u8>(fbits)), Imm8(static_cast<u8>(rounding)));
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorGreater(size_t esize, const U128& a, const U128& b) {
@ -2364,7 +2266,6 @@ U128 IREmitter::FPVectorGreater(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorGreater64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b) {
@ -2375,7 +2276,6 @@ U128 IREmitter::FPVectorGreaterEqual(size_t esize, const U128& a, const U128& b)
return Inst<U128>(Opcode::FPVectorGreaterEqual64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorMax(size_t esize, const U128& a, const U128& b) {
@ -2386,7 +2286,6 @@ U128 IREmitter::FPVectorMax(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorMax64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorMin(size_t esize, const U128& a, const U128& b) {
@ -2397,7 +2296,6 @@ U128 IREmitter::FPVectorMin(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorMin64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b) {
@ -2408,7 +2306,6 @@ U128 IREmitter::FPVectorMul(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorMul64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const U128& c) {
@ -2421,7 +2318,6 @@ U128 IREmitter::FPVectorMulAdd(size_t esize, const U128& a, const U128& b, const
return Inst<U128>(Opcode::FPVectorMulAdd64, a, b, c);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorMulX(size_t esize, const U128& a, const U128& b) {
@ -2432,7 +2328,6 @@ U128 IREmitter::FPVectorMulX(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorMulX64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorNeg(size_t esize, const U128& a) {
@ -2445,7 +2340,6 @@ U128 IREmitter::FPVectorNeg(size_t esize, const U128& a) {
return Inst<U128>(Opcode::FPVectorNeg64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorPairedAdd(size_t esize, const U128& a, const U128& b) {
@ -2456,7 +2350,6 @@ U128 IREmitter::FPVectorPairedAdd(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorPairedAdd64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128& b) {
@ -2467,7 +2360,6 @@ U128 IREmitter::FPVectorPairedAddLower(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::FPVectorPairedAddLower64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
@ -2480,7 +2372,6 @@ U128 IREmitter::FPVectorRecipEstimate(size_t esize, const U128& a) {
return Inst<U128>(Opcode::FPVectorRecipEstimate64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128& b) {
@ -2493,7 +2384,6 @@ U128 IREmitter::FPVectorRecipStepFused(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::FPVectorRecipStepFused64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRoundInt(size_t esize, const U128& operand, FP::RoundingMode rounding, bool exact) {
@ -2509,7 +2399,6 @@ U128 IREmitter::FPVectorRoundInt(size_t esize, const U128& operand, FP::Rounding
return Inst<U128>(Opcode::FPVectorRoundInt64, operand, rounding_imm, exact_imm);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
@ -2522,7 +2411,6 @@ U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
return Inst<U128>(Opcode::FPVectorRSqrtEstimate64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128& b) {
@ -2535,7 +2423,6 @@ U128 IREmitter::FPVectorRSqrtStepFused(size_t esize, const U128& a, const U128&
return Inst<U128>(Opcode::FPVectorRSqrtStepFused64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorSqrt(size_t esize, const U128& a) {
@ -2546,7 +2433,6 @@ U128 IREmitter::FPVectorSqrt(size_t esize, const U128& a) {
return Inst<U128>(Opcode::FPVectorSqrt64, a);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
@ -2557,7 +2443,6 @@ U128 IREmitter::FPVectorSub(size_t esize, const U128& a, const U128& b) {
return Inst<U128>(Opcode::FPVectorSub64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
@ -2576,7 +2461,6 @@ U128 IREmitter::FPVectorToSignedFixed(size_t esize, const U128& a, size_t fbits,
}
UNREACHABLE();
return {};
}
U128 IREmitter::FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbits, FP::RoundingMode rounding) {
@ -2595,7 +2479,6 @@ U128 IREmitter::FPVectorToUnsignedFixed(size_t esize, const U128& a, size_t fbit
}
UNREACHABLE();
return {};
}
void IREmitter::Breakpoint() {

3
src/frontend/ir/microinstruction.cpp
View file

@ -567,8 +567,7 @@ Inst* Inst::GetAssociatedPseudoOperation(Opcode opcode) {
break;
}
ASSERT_MSG(false, "Not a valid pseudo-operation");
return nullptr;
ASSERT_FALSE("Not a valid pseudo-operation");
}
Type Inst::GetType() const {