A64: Implement load/store single structure instructions
Implements LD{1, 2, 3, 4}, LD{1, 2, 3, 4}R, and ST{1, 2, 3, 4} single
structure variants.
This commit is contained in:
Lioncash
MerryMage
parent
b6e223fc58
commit
593eca7fb1
4 changed files with 256 additions and 40 deletions
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@ -100,6 +100,7 @@ add_library(dynarmic
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frontend/A64/translate/impl/load_store_register_pair.cpp
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frontend/A64/translate/impl/load_store_register_register_offset.cpp
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frontend/A64/translate/impl/load_store_register_unprivileged.cpp
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frontend/A64/translate/impl/load_store_single_structure.cpp
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frontend/A64/translate/impl/move_wide.cpp
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frontend/A64/translate/impl/simd_aes.cpp
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frontend/A64/translate/impl/simd_copy.cpp
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@ -109,30 +109,30 @@ INST(LDx_mult_1, "LDx (multiple structures)", "0Q001
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INST(LDx_mult_2, "LDx (multiple structures)", "0Q001100110mmmmmoooozznnnnnttttt")
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// Loads and stores - Advanced SIMD Load/Store single structures
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//INST(ST1_sngl_1, "ST1 (single structure)", "0Q00110100000000--0Szznnnnnttttt")
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//INST(ST1_sngl_2, "ST1 (single structure)", "0Q001101100mmmmm--0Szznnnnnttttt")
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//INST(ST3_sngl_1, "ST3 (single structure)", "0Q00110100000000--1Szznnnnnttttt")
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//INST(ST3_sngl_2, "ST3 (single structure)", "0Q001101100mmmmm--1Szznnnnnttttt")
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//INST(ST2_sngl_1, "ST2 (single structure)", "0Q00110100100000--0Szznnnnnttttt")
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//INST(ST2_sngl_2, "ST2 (single structure)", "0Q001101101mmmmm--0Szznnnnnttttt")
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//INST(ST4_sngl_1, "ST4 (single structure)", "0Q00110100100000--1Szznnnnnttttt")
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//INST(ST4_sngl_2, "ST4 (single structure)", "0Q001101101mmmmm--1Szznnnnnttttt")
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//INST(LD1_sngl_1, "LD1 (single structure)", "0Q00110101000000--0Szznnnnnttttt")
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//INST(LD1_sngl_2, "LD1 (single structure)", "0Q001101110mmmmm--0Szznnnnnttttt")
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//INST(LD3_sngl_1, "LD3 (single structure)", "0Q00110101000000--1Szznnnnnttttt")
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//INST(LD3_sngl_2, "LD3 (single structure)", "0Q001101110mmmmm--1Szznnnnnttttt")
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//INST(LD1R_1, "LD1R", "0Q001101010000001100zznnnnnttttt")
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//INST(LD1R_2, "LD1R", "0Q001101110mmmmm1100zznnnnnttttt")
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//INST(LD3R_1, "LD3R", "0Q001101010000001110zznnnnnttttt")
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//INST(LD3R_2, "LD3R", "0Q001101110mmmmm1110zznnnnnttttt")
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//INST(LD2_sngl_1, "LD2 (single structure)", "0Q00110101100000--0Szznnnnnttttt")
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//INST(LD2_sngl_2, "LD2 (single structure)", "0Q001101111mmmmm--0Szznnnnnttttt")
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//INST(LD4_sngl_1, "LD4 (single structure)", "0Q00110101100000--1Szznnnnnttttt")
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//INST(LD4_sngl_2, "LD4 (single structure)", "0Q001101111mmmmm--1Szznnnnnttttt")
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//INST(LD2R_1, "LD2R", "0Q001101011000001100zznnnnnttttt")
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//INST(LD2R_2, "LD2R", "0Q001101111mmmmm1100zznnnnnttttt")
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//INST(LD4R_1, "LD4R", "0Q001101011000001110zznnnnnttttt")
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//INST(LD4R_2, "LD4R", "0Q001101111mmmmm1110zznnnnnttttt")
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INST(ST1_sngl_1, "ST1 (single structure)", "0Q00110100000000oo0Szznnnnnttttt")
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INST(ST1_sngl_2, "ST1 (single structure)", "0Q001101100mmmmmoo0Szznnnnnttttt")
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INST(ST3_sngl_1, "ST3 (single structure)", "0Q00110100000000oo1Szznnnnnttttt")
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INST(ST3_sngl_2, "ST3 (single structure)", "0Q001101100mmmmmoo1Szznnnnnttttt")
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INST(ST2_sngl_1, "ST2 (single structure)", "0Q00110100100000oo0Szznnnnnttttt")
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INST(ST2_sngl_2, "ST2 (single structure)", "0Q001101101mmmmmoo0Szznnnnnttttt")
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INST(ST4_sngl_1, "ST4 (single structure)", "0Q00110100100000oo1Szznnnnnttttt")
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INST(ST4_sngl_2, "ST4 (single structure)", "0Q001101101mmmmmoo1Szznnnnnttttt")
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INST(LD1_sngl_1, "LD1 (single structure)", "0Q00110101000000oo0Szznnnnnttttt")
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INST(LD1_sngl_2, "LD1 (single structure)", "0Q001101110mmmmmoo0Szznnnnnttttt")
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INST(LD3_sngl_1, "LD3 (single structure)", "0Q00110101000000oo1Szznnnnnttttt")
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INST(LD3_sngl_2, "LD3 (single structure)", "0Q001101110mmmmmoo1Szznnnnnttttt")
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INST(LD1R_1, "LD1R", "0Q001101010000001100zznnnnnttttt")
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INST(LD1R_2, "LD1R", "0Q001101110mmmmm1100zznnnnnttttt")
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INST(LD3R_1, "LD3R", "0Q001101010000001110zznnnnnttttt")
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INST(LD3R_2, "LD3R", "0Q001101110mmmmm1110zznnnnnttttt")
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INST(LD2_sngl_1, "LD2 (single structure)", "0Q00110101100000oo0Szznnnnnttttt")
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INST(LD2_sngl_2, "LD2 (single structure)", "0Q001101111mmmmmoo0Szznnnnnttttt")
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INST(LD4_sngl_1, "LD4 (single structure)", "0Q00110101100000oo1Szznnnnnttttt")
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INST(LD4_sngl_2, "LD4 (single structure)", "0Q001101111mmmmmoo1Szznnnnnttttt")
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INST(LD2R_1, "LD2R", "0Q001101011000001100zznnnnnttttt")
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INST(LD2R_2, "LD2R", "0Q001101111mmmmm1100zznnnnnttttt")
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INST(LD4R_1, "LD4R", "0Q001101011000001110zznnnnnttttt")
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INST(LD4R_2, "LD4R", "0Q001101111mmmmm1110zznnnnnttttt")
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// Loads and stores - Load/Store Exclusive
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INST(STXR, "STXRB, STXRH, STXR", "zz001000000sssss011111nnnnnttttt")
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@ -182,26 +182,26 @@ struct TranslatorVisitor final {
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bool LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt);
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// Loads and stores - Advanced SIMD Load/Store single structures
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bool ST1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST1_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST3_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST3_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST2_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST2_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST4_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST4_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD1_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD1_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD3_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD3_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
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bool LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
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bool LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
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bool LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
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bool LD2_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD2_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD4_sngl_1(bool Q, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD4_sngl_2(bool Q, Reg Rm, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt);
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bool LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
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bool LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt);
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bool LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt);
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215
src/frontend/A64/translate/impl/load_store_single_structure.cpp
Normal file
215
src/frontend/A64/translate/impl/load_store_single_structure.cpp
Normal file
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@ -0,0 +1,215 @@
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/* This file is part of the dynarmic project.
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* Copyright (c) 2018 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <boost/optional.hpp>
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#include "frontend/A64/translate/impl/impl.h"
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namespace Dynarmic::A64 {
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static bool SharedDecodeAndOperation(TranslatorVisitor& tv, IREmitter& ir, bool wback, MemOp memop,
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bool Q, bool S, bool R, bool replicate, boost::optional<Reg> Rm,
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Imm<3> opcode, Imm<2> size, Reg Rn, Vec Vt) {
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const size_t selem = (opcode.Bit<0>() << 1 | u32{R}) + 1;
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size_t scale = opcode.Bits<1, 2>();
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size_t index = 0;
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switch (scale) {
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case 0:
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index = Q << 3 | S << 2 | size.ZeroExtend();
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break;
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case 1:
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if (size.Bit<0>()) {
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return tv.UnallocatedEncoding();
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}
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index = Q << 2 | S << 1 | u32{size.Bit<1>()};
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break;
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case 2:
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if (size.Bit<1>()) {
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return tv.UnallocatedEncoding();
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}
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if (size.Bit<0>()) {
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if (S) {
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return tv.UnallocatedEncoding();
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}
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index = Q;
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scale = 3;
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} else {
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index = Q << 1 | u32{S};
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}
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break;
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case 3:
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if (memop == MemOp::STORE || S) {
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return tv.UnallocatedEncoding();
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}
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scale = size.ZeroExtend();
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break;
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}
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const size_t datasize = Q ? 128 : 64;
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const size_t esize = 8 << scale;
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const size_t ebytes = esize / 8;
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IR::U64 address;
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if (Rn == Reg::SP)
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// TODO: Check SP Alignment
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address = tv.SP(64);
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else
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address = tv.X(64, Rn);
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IR::U64 offs = ir.Imm64(0);
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if (replicate) {
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for (size_t s = 0; s < selem; s++) {
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const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32);
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const IR::UAnyU128 element = tv.Mem(ir.Add(address, offs), ebytes, AccType::VEC);
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const IR::U128 broadcasted_element = ir.VectorBroadcast(esize, element);
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tv.V(datasize, tt, broadcasted_element);
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offs = ir.Add(offs, ir.Imm64(ebytes));
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}
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} else {
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for (size_t s = 0; s < selem; s++) {
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const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32);
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const IR::U128 rval = tv.V(128, tt);
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if (memop == MemOp::LOAD) {
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const IR::UAny elem = tv.Mem(ir.Add(address, offs), ebytes, AccType::VEC);
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const IR::U128 vec = ir.VectorSetElement(esize, rval, index, elem);
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tv.V(128, tt, vec);
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} else {
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const IR::UAny elem = ir.VectorGetElement(esize, rval, index);
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tv.Mem(ir.Add(address, offs), ebytes, AccType::VEC, elem);
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}
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offs = ir.Add(offs, ir.Imm64(ebytes));
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}
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}
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if (wback) {
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if (*Rm != Reg::SP)
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offs = tv.X(64, *Rm);
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if (Rn == Reg::SP)
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tv.SP(64, ir.Add(address, offs));
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else
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tv.X(64, Rn, ir.Add(address, offs));
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}
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return true;
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}
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bool TranslatorVisitor::LD1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, S, false, false, {},
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Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, S, false, false, Rm,
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Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, false, false, true, {}, Imm<3>{0b110}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, false, false, true, Rm, Imm<3>{0b110}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, S, true, false, {},
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Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, S, true, false, Rm,
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Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, false, true, true, {}, Imm<3>{0b110}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, false, true, true, Rm, Imm<3>{0b110}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, S, false, false, {},
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Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, S, false, false, Rm,
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Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, false, false, true, {}, Imm<3>{0b111}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, false, false, true, Rm, Imm<3>{0b111}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, S, true, false, {},
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Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, S, true, false, Rm,
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Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
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}
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bool TranslatorVisitor::LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
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return SharedDecodeAndOperation(*this, ir, false, MemOp::LOAD, Q, false, true, true, {}, Imm<3>{0b111}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::LD4R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, true, MemOp::LOAD, Q, false, true, true, Rm, Imm<3>{0b111}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, false, MemOp::STORE, Q, S, false, false, {},
|
||||
Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, true, MemOp::STORE, Q, S, false, false, Rm,
|
||||
Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, false, MemOp::STORE, Q, S, true, false, {},
|
||||
Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, true, MemOp::STORE, Q, S, true, false, Rm,
|
||||
Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, false, MemOp::STORE, Q, S, false, false, {},
|
||||
Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, true, MemOp::STORE, Q, S, false, false, Rm,
|
||||
Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, false, MemOp::STORE, Q, S, true, false, {},
|
||||
Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
bool TranslatorVisitor::ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
|
||||
return SharedDecodeAndOperation(*this, ir, true, MemOp::STORE, Q, S, true, false, Rm,
|
||||
Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt);
|
||||
}
|
||||
|
||||
} // namespace Dynarmic::A64
|
||||
Loading…
Reference in a new issue