From 586b00d11d273bd8bd9ee0dde6b8923cb350cce1 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 23 Mar 2018 12:01:42 -0400 Subject: [PATCH] A64: Implement REV64 --- src/frontend/A64/decoder/a64.inc | 2 +- .../impl/simd_scalar_two_register_misc.cpp | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index e51e7b54..11e50606 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -565,7 +565,7 @@ INST(INS_elt, "INS (element)", "01101 //INST(FCADD_vec, "FCADD", "0Q101110zz0mmmmm111r01nnnnnddddd") // Data Processing - FP and SIMD - SIMD Two-register misc -//INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd") +INST(REV64_asimd, "REV64", "0Q001110zz100000000010nnnnnddddd") INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd") //INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd") //INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index 026563af..faddce44 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -55,6 +55,40 @@ bool TranslatorVisitor::REV32_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::REV64_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) { + const u32 zext_size = size.ZeroExtend(); + + if (zext_size >= 3) { + return UnallocatedEncoding(); + } + + const size_t datasize = Q ? 128 : 64; + const size_t esize = 16 << zext_size; + const u8 shift = static_cast(8 << zext_size); + + const IR::U128 data = V(datasize, Vn); + + // TODO: Consider factoring byte swapping code out into its own opcode. + // Technically the rest of the following code can be a PSHUFB + // in the presence of SSSE3. + IR::U128 result = ir.VectorOr(ir.VectorLogicalShiftRight(esize, data, shift), + ir.VectorLogicalShiftLeft(esize, data, shift)); + + switch (zext_size) { + case 0: // 8-bit elements + result = ir.VectorShuffleLowHalfwords(result, 0b00011011); + result = ir.VectorShuffleHighHalfwords(result, 0b00011011); + break; + case 1: // 16-bit elements + result = ir.VectorShuffleLowHalfwords(result, 0b01001110); + result = ir.VectorShuffleHighHalfwords(result, 0b01001110); + break; + } + + V(datasize, Vd, result); + return true; +} + bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const auto esize = sz ? 64 : 32;