diff --git a/src/frontend/translate/translate_arm/multiply.cpp b/src/frontend/translate/translate_arm/multiply.cpp
index 2ef8b70f..c41569c7 100644
--- a/src/frontend/translate/translate_arm/multiply.cpp
+++ b/src/frontend/translate/translate_arm/multiply.cpp
@@ -171,15 +171,53 @@ bool ArmTranslatorVisitor::arm_SMULWy(Cond cond, Reg d, Reg m, bool M, Reg n) {
 
 // Multiply (Most significant word) instructions
 bool ArmTranslatorVisitor::arm_SMMLA(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) {
-    return InterpretThisInstruction();
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC /* no check for a */)
+        return UnpredictableInstruction();
+    if (ConditionPassed(cond)) {
+        auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
+        auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
+        auto a64 = ir.Pack2x32To1x64(ir.Imm32(0), ir.GetRegister(a));
+        auto temp = ir.Add64(a64, ir.Mul64(n64, m64));
+        auto result_carry = ir.MostSignificantWord(temp);
+        auto result = result_carry.result;
+        if (R)
+            result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
+        ir.SetRegister(d, result);
+    }
+    return true;
 }
 
 bool ArmTranslatorVisitor::arm_SMMLS(Cond cond, Reg d, Reg a, Reg m, bool R, Reg n) {
-    return InterpretThisInstruction();
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC || a == Reg::PC)
+        return UnpredictableInstruction();
+    if (ConditionPassed(cond)) {
+        auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
+        auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
+        auto a64 = ir.Pack2x32To1x64(ir.Imm32(0), ir.GetRegister(a));
+        auto temp = ir.Sub64(a64, ir.Mul64(n64, m64));
+        auto result_carry = ir.MostSignificantWord(temp);
+        auto result = result_carry.result;
+        if (R)
+            result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
+        ir.SetRegister(d, result);
+    }
+    return true;
 }
 
 bool ArmTranslatorVisitor::arm_SMMUL(Cond cond, Reg d, Reg m, bool R, Reg n) {
-    return InterpretThisInstruction();
+    if (d == Reg::PC || n == Reg::PC || m == Reg::PC)
+        return UnpredictableInstruction();
+    if (ConditionPassed(cond)) {
+        auto n64 = ir.SignExtendWordToLong(ir.GetRegister(n));
+        auto m64 = ir.SignExtendWordToLong(ir.GetRegister(m));
+        auto product = ir.Mul64(n64, m64);
+        auto result_carry = ir.MostSignificantWord(product);
+        auto result = result_carry.result;
+        if (R)
+            result = ir.AddWithCarry(result, ir.Imm32(0), result_carry.carry).result;
+        ir.SetRegister(d, result);
+    }
+    return true;
 }
 
 
diff --git a/tests/arm/fuzz_arm.cpp b/tests/arm/fuzz_arm.cpp
index 45edc948..3d8719bd 100644
--- a/tests/arm/fuzz_arm.cpp
+++ b/tests/arm/fuzz_arm.cpp
@@ -727,7 +727,7 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64]") {
                Dynarmic::Common::Bits<12, 15>(inst) != Dynarmic::Common::Bits<16, 19>(inst);
     };
 
-    const std::array<InstructionGenerator, 7> instructions = {
+    const std::array<InstructionGenerator, 10> instructions = {
             {
                     InstructionGenerator("cccc0000001Sddddaaaammmm1001nnnn", validate_d_a_m_n), // MLA
                     InstructionGenerator("cccc0000000Sdddd0000mmmm1001nnnn", validate_d_m_n),   // MUL
@@ -737,6 +737,24 @@ TEST_CASE("Fuzz ARM multiply instructions", "[JitX64]") {
                     InstructionGenerator("cccc00000100ddddaaaammmm1001nnnn", validate_h_l_m_n), // UMAAL
                     InstructionGenerator("cccc0000101Sddddaaaammmm1001nnnn", validate_h_l_m_n), // UMLAL
                     InstructionGenerator("cccc0000100Sddddaaaammmm1001nnnn", validate_h_l_m_n), // UMULL
+
+                    //InstructionGenerator("cccc00010100ddddaaaammmm1xy0nnnn", validate_d_a_m_n), // SMLALxy
+                    //InstructionGenerator("cccc00010000ddddaaaammmm1xy0nnnn", validate_d_a_m_n), // SMLAxy
+                    //InstructionGenerator("cccc00010110dddd0000mmmm1xy0nnnn", validate_d_m_n),   // SMULxy
+
+                    //InstructionGenerator("cccc00010010ddddaaaammmm1y00nnnn", validate_d_a_m_n), // SMLAWy
+                    //InstructionGenerator("cccc00010010dddd0000mmmm1y10nnnn", validate_d_m_n),   // SMULWy
+
+                    InstructionGenerator("cccc01110101dddd1111mmmm00R1nnnn", validate_d_m_n),   // SMMUL
+                    InstructionGenerator("cccc01110101ddddaaaammmm00R1nnnn", validate_d_a_m_n), // SMMLA
+                    InstructionGenerator("cccc01110101ddddaaaammmm11R1nnnn", validate_d_a_m_n), // SMMLS
+
+                    //InstructionGenerator("cccc01110000ddddaaaammmm00M1nnnn", validate_d_a_m_n), // SMLAD
+                    //InstructionGenerator("cccc01110100ddddaaaammmm00M1nnnn", validate_d_a_m_n), // SMLALD
+                    //InstructionGenerator("cccc01110000ddddaaaammmm01M1nnnn", validate_d_a_m_n), // SMLSD
+                    //InstructionGenerator("cccc01110100ddddaaaammmm01M1nnnn", validate_d_a_m_n), // SMLSLD
+                    //InstructionGenerator("cccc01110000dddd1111mmmm00M1nnnn", validate_d_m_n),   // SMUAD
+                    //InstructionGenerator("cccc01110000dddd1111mmmm01M1nnnn", validate_d_m_n),   // SMUSD
             }
     };