Merge pull request #588 from lioncash/store
thumb32: Implement STRB{T}/STRH{T}/STR{T} immediate variants
This commit is contained in:
merry
GitHub
commit
54c481c8bd
3 changed files with 198 additions and 12 deletions
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@ -124,20 +124,20 @@ INST(thumb32_UDF, "Invalid decoding", "11110-111-------10-0--
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INST(thumb32_B_cond, "B (cond)", "11110Sccccvvvvvv10i0ivvvvvvvvvvv")
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// Store Single Data Item
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//INST(thumb32_STRB_imm_1, "STRB (imm)", "111110000000--------1--1--------")
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//INST(thumb32_STRB_imm_2, "STRB (imm)", "111110000000--------1100--------")
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//INST(thumb32_STRB_imm_3, "STRB (imm)", "111110001000--------------------")
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//INST(thumb32_STRBT, "STRBT", "111110000000--------1110--------")
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INST(thumb32_STRB_imm_1, "STRB (imm)", "111110000000nnnntttt1PU1iiiiiiii")
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INST(thumb32_STRB_imm_2, "STRB (imm)", "111110000000nnnntttt1100iiiiiiii")
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INST(thumb32_STRB_imm_3, "STRB (imm)", "111110001000nnnnttttiiiiiiiiiiii")
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INST(thumb32_STRBT, "STRBT", "111110000000nnnntttt1110iiiiiiii")
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INST(thumb32_STRB, "STRB (reg)", "111110000000nnnntttt000000iimmmm")
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//INST(thumb32_STRH_imm_1, "STRH (imm)", "111110000010--------1--1--------")
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//INST(thumb32_STRH_imm_2, "STRH (imm)", "111110000010--------1100--------")
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//INST(thumb32_STRH_imm_3, "STRH (imm)", "111110001010--------------------")
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//INST(thumb32_STRHT, "STRHT", "111110000010--------1110--------")
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INST(thumb32_STRH_imm_1, "STRH (imm)", "111110000010nnnntttt1PU1iiiiiiii")
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INST(thumb32_STRH_imm_2, "STRH (imm)", "111110000010nnnntttt1100iiiiiiii")
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INST(thumb32_STRH_imm_3, "STRH (imm)", "111110001010nnnnttttiiiiiiiiiiii")
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INST(thumb32_STRHT, "STRHT", "111110000010nnnntttt1110iiiiiiii")
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INST(thumb32_STRH, "STRH (reg)", "111110000010nnnntttt000000iimmmm")
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//INST(thumb32_STR_imm_1, "STR (imm)", "111110000100--------1--1--------")
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//INST(thumb32_STR_imm_2, "STR (imm)", "111110000100--------1100--------")
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//INST(thumb32_STR_imm_3, "STR (imm)", "111110001100--------------------")
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//INST(thumb32_STRT, "STRT", "111110000100--------1110--------")
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INST(thumb32_STR_imm_1, "STR (imm)", "111110000100nnnntttt1PU1iiiiiiii")
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INST(thumb32_STR_imm_2, "STR (imm)", "111110000100nnnntttt1100iiiiiiii")
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INST(thumb32_STR_imm_3, "STR (imm)", "111110001100nnnnttttiiiiiiiiiiii")
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INST(thumb32_STRT, "STRT", "111110000100nnnntttt1110iiiiiiii")
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INST(thumb32_STR_reg, "STR (reg)", "111110000100nnnntttt000000iimmmm")
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// Load Byte and Memory Hints
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@ -29,18 +29,192 @@ static bool StoreRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2,
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return true;
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}
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using StoreImmFn = void (*)(ThumbTranslatorVisitor&, const IR::U32&, const IR::U32&);
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static void StoreImmByteFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) {
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v.ir.WriteMemory8(address, v.ir.LeastSignificantByte(data));
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}
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static void StoreImmHalfFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) {
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v.ir.WriteMemory16(address, v.ir.LeastSignificantHalf(data));
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}
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static void StoreImmWordFn(ThumbTranslatorVisitor& v, const IR::U32& address, const IR::U32& data) {
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v.ir.WriteMemory32(address, data);
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}
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static bool StoreImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W, Imm<12> imm12,
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StoreImmFn store_fn) {
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const auto imm32 = imm12.ZeroExtend();
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const auto reg_n = v.ir.GetRegister(n);
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const auto reg_t = v.ir.GetRegister(t);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm32));
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const IR::U32 address = P ? offset_address
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: reg_n;
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store_fn(v, address, reg_t);
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC || n == t) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmByteFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRBT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution levels.
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat this as a normal STRB, given we don't support
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// execution levels other than EL0 currently.
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return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmByteFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) {
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ir.WriteMemory8(offset_address, ir.LeastSignificantByte(data));
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});
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}
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bool ThumbTranslatorVisitor::thumb32_STRH_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC || n == t) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRH_imm_2(Reg n, Reg t, Imm<8> imm8) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRH_imm_3(Reg n, Reg t, Imm<12> imm12) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmHalfFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRHT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution levels.
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat this as a normal STRH, given we don't support
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// execution levels other than EL0 currently.
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return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmHalfFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) {
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ir.WriteMemory16(offset_address, ir.LeastSignificantHalf(data));
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});
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}
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bool ThumbTranslatorVisitor::thumb32_STR_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC || n == t) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, P, U, true, Imm<12>{imm8.ZeroExtend()}, StoreImmWordFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STR_imm_2(Reg n, Reg t, Imm<8> imm8) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, true, false, false, Imm<12>{imm8.ZeroExtend()}, StoreImmWordFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STR_imm_3(Reg n, Reg t, Imm<12> imm12) {
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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return StoreImmediate(*this, n, t, true, true, false, imm12, StoreImmWordFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STRT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution levels.
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if (n == Reg::PC) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat this as a normal STR, given we don't support
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// execution levels other than EL0 currently.
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return StoreImmediate(*this, n, t, true, true, false, Imm<12>{imm8.ZeroExtend()}, StoreImmWordFn);
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}
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bool ThumbTranslatorVisitor::thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return StoreRegister(*this, n, t, imm2, m, [this](const IR::U32& offset_address, const IR::U32& data) {
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ir.WriteMemory32(offset_address, data);
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@ -243,8 +243,20 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_B_cond(Imm<1> S, Cond cond, Imm<6> hi, Imm<1> j1, Imm<1> j2, Imm<11> lo);
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// thumb32 store single data item instructions
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bool thumb32_STRB_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8);
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bool thumb32_STRB_imm_2(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_STRB_imm_3(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_STRBT(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_STRB(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_STRH_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8);
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bool thumb32_STRH_imm_2(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_STRH_imm_3(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_STRHT(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_STRH(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_STR_imm_1(Reg n, Reg t, bool P, bool U, Imm<8> imm8);
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bool thumb32_STR_imm_2(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_STR_imm_3(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_STRT(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_STR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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// thumb32 load byte and memory hints
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