From 4f1f7c8e975d72e54f6dfa3b6cfbb19d0e1b7dc8 Mon Sep 17 00:00:00 2001 From: Merry Date: Tue, 29 Nov 2022 15:11:00 +0000 Subject: [PATCH] arm64/reg_alloc: Remove PrepareForCallReg and PrepareForCallVec --- .../arm64/emit_arm64_a32_coprocessor.cpp | 17 ++++---------- .../backend/arm64/emit_arm64_a32_memory.cpp | 12 +++++----- src/dynarmic/backend/arm64/emit_arm64_a64.cpp | 4 ++-- .../backend/arm64/emit_arm64_a64_memory.cpp | 22 ++++++++++--------- src/dynarmic/backend/arm64/reg_alloc.cpp | 14 ------------ src/dynarmic/backend/arm64/reg_alloc.h | 2 -- 6 files changed, 24 insertions(+), 47 deletions(-) diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp index 629c381c..5115fbbb 100644 --- a/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp +++ b/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp @@ -24,19 +24,6 @@ static void EmitCoprocessorException() { } static void CallCoprocCallback(oaknut::CodeGenerator& code, EmitContext& ctx, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional arg0 = {}, std::optional arg1 = {}) { - if (inst) { - const auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, arg0, arg1); - - if (callback.user_arg) { - code.MOV(X0, reinterpret_cast(*callback.user_arg)); - } - - code.MOV(Xscratch0, reinterpret_cast(callback.function)); - code.BLR(Xscratch0); - code.MOV(Xresult, X0); - return; - } - ctx.reg_alloc.PrepareForCall({}, arg0, arg1); if (callback.user_arg) { @@ -45,6 +32,10 @@ static void CallCoprocCallback(oaknut::CodeGenerator& code, EmitContext& ctx, A3 code.MOV(Xscratch0, reinterpret_cast(callback.function)); code.BLR(Xscratch0); + + if (inst) { + ctx.reg_alloc.DefineAsRegister(inst, X0); + } } template<> diff --git a/src/dynarmic/backend/arm64/emit_arm64_a32_memory.cpp b/src/dynarmic/backend/arm64/emit_arm64_a32_memory.cpp index 1cf5f774..8d72dd19 100644 --- a/src/dynarmic/backend/arm64/emit_arm64_a32_memory.cpp +++ b/src/dynarmic/backend/arm64/emit_arm64_a32_memory.cpp @@ -25,19 +25,19 @@ static bool IsOrdered(IR::AccType acctype) { static void EmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, args[1]); + ctx.reg_alloc.PrepareForCall({}, args[1]); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); EmitRelocation(code, ctx, fn); if (ordered) { code.DMB(oaknut::BarrierOp::ISH); } - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } static void EmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, args[1]); + ctx.reg_alloc.PrepareForCall({}, args[1]); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); code.MOV(Wscratch0, 1); @@ -46,7 +46,7 @@ static void EmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ct if (ordered) { code.DMB(oaknut::BarrierOp::ISH); } - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } static void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { @@ -65,7 +65,7 @@ static void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::I static void EmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, args[1], args[2]); + ctx.reg_alloc.PrepareForCall({}, args[1], args[2]); const bool ordered = IsOrdered(args[3].GetImmediateAccType()); oaknut::Label end; @@ -81,7 +81,7 @@ static void EmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& c code.DMB(oaknut::BarrierOp::ISH); } code.l(end); - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } template<> diff --git a/src/dynarmic/backend/arm64/emit_arm64_a64.cpp b/src/dynarmic/backend/arm64/emit_arm64_a64.cpp index a0f2fac9..a686f555 100644 --- a/src/dynarmic/backend/arm64/emit_arm64_a64.cpp +++ b/src/dynarmic/backend/arm64/emit_arm64_a64.cpp @@ -423,7 +423,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& template<> void EmitIR(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst); + ctx.reg_alloc.PrepareForCall(); if (!ctx.conf.wall_clock_cntpct && ctx.conf.enable_cycle_counting) { code.LDR(X1, SP, offsetof(StackLayout, cycles_to_run)); code.SUB(X1, X1, Xticks); @@ -433,7 +433,7 @@ void EmitIR(oaknut::CodeGenerator& code, EmitContext& code.MOV(Xticks, X0); } EmitRelocation(code, ctx, LinkTarget::GetCNTPCT); - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } template<> diff --git a/src/dynarmic/backend/arm64/emit_arm64_a64_memory.cpp b/src/dynarmic/backend/arm64/emit_arm64_a64_memory.cpp index 55c185b7..bf378605 100644 --- a/src/dynarmic/backend/arm64/emit_arm64_a64_memory.cpp +++ b/src/dynarmic/backend/arm64/emit_arm64_a64_memory.cpp @@ -25,31 +25,32 @@ static bool IsOrdered(IR::AccType acctype) { static void EmitReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, args[1]); + ctx.reg_alloc.PrepareForCall({}, args[1]); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); EmitRelocation(code, ctx, fn); if (ordered) { code.DMB(oaknut::BarrierOp::ISH); } - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } static void EmitReadMemory128(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Qresult = ctx.reg_alloc.PrepareForCallVec(inst, {}, args[1]); + ctx.reg_alloc.PrepareForCall({}, args[1]); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); EmitRelocation(code, ctx, fn); if (ordered) { code.DMB(oaknut::BarrierOp::ISH); } - code.MOV(Qresult.B16(), Q0.B16()); + code.MOV(Q8.B16(), Q0.B16()); + ctx.reg_alloc.DefineAsRegister(inst, Q8); } static void EmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, args[1]); + ctx.reg_alloc.PrepareForCall({}, args[1]); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); code.MOV(Wscratch0, 1); @@ -58,12 +59,12 @@ static void EmitExclusiveReadMemory(oaknut::CodeGenerator& code, EmitContext& ct if (ordered) { code.DMB(oaknut::BarrierOp::ISH); } - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } static void EmitExclusiveReadMemory128(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Qresult = ctx.reg_alloc.PrepareForCallVec(inst, {}, args[1]); + ctx.reg_alloc.PrepareForCall({}, args[1]); const bool ordered = IsOrdered(args[2].GetImmediateAccType()); code.MOV(Wscratch0, 1); @@ -72,7 +73,8 @@ static void EmitExclusiveReadMemory128(oaknut::CodeGenerator& code, EmitContext& if (ordered) { code.DMB(oaknut::BarrierOp::ISH); } - code.MOV(Qresult.B16(), Q0.B16()); + code.MOV(Q8.B16(), Q0.B16()); + ctx.reg_alloc.DefineAsRegister(inst, Q8); } static void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { @@ -91,7 +93,7 @@ static void EmitWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::I static void EmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, LinkTarget fn) { auto args = ctx.reg_alloc.GetArgumentInfo(inst); - auto Xresult = ctx.reg_alloc.PrepareForCallReg(inst, {}, args[1], args[2]); + ctx.reg_alloc.PrepareForCall({}, args[1], args[2]); const bool ordered = IsOrdered(args[3].GetImmediateAccType()); oaknut::Label end; @@ -107,7 +109,7 @@ static void EmitExclusiveWriteMemory(oaknut::CodeGenerator& code, EmitContext& c code.DMB(oaknut::BarrierOp::ISH); } code.l(end); - code.MOV(Xresult, X0); + ctx.reg_alloc.DefineAsRegister(inst, X0); } template<> diff --git a/src/dynarmic/backend/arm64/reg_alloc.cpp b/src/dynarmic/backend/arm64/reg_alloc.cpp index e40216c9..3e61532a 100644 --- a/src/dynarmic/backend/arm64/reg_alloc.cpp +++ b/src/dynarmic/backend/arm64/reg_alloc.cpp @@ -182,20 +182,6 @@ void RegAlloc::PrepareForCall(std::optional arg0, } } -oaknut::XReg RegAlloc::PrepareForCallReg(IR::Inst* result, std::optional arg0, std::optional arg1, std::optional arg2, std::optional arg3) { - PrepareForCall(arg0, arg1, arg2, arg3); - ASSERT(result && result->GetType() != IR::Type::U128); - DefineAsRegister(result, X0); - return X0; -} - -oaknut::QReg RegAlloc::PrepareForCallVec(IR::Inst* result, std::optional arg0, std::optional arg1, std::optional arg2, std::optional arg3) { - PrepareForCall(arg0, arg1, arg2, arg3); - ASSERT(result && result->GetType() == IR::Type::U128); - DefineAsRegister(result, Q8); - return Q8; -} - void RegAlloc::DefineAsExisting(IR::Inst* inst, Argument& arg) { ASSERT(!ValueLocation(inst)); diff --git a/src/dynarmic/backend/arm64/reg_alloc.h b/src/dynarmic/backend/arm64/reg_alloc.h index 4d5c3fe7..a101ee6d 100644 --- a/src/dynarmic/backend/arm64/reg_alloc.h +++ b/src/dynarmic/backend/arm64/reg_alloc.h @@ -272,8 +272,6 @@ public: } void PrepareForCall(std::optional arg0 = {}, std::optional arg1 = {}, std::optional arg2 = {}, std::optional arg3 = {}); - oaknut::XReg PrepareForCallReg(IR::Inst* result, std::optional arg0 = {}, std::optional arg1 = {}, std::optional arg2 = {}, std::optional arg3 = {}); - oaknut::QReg PrepareForCallVec(IR::Inst* result, std::optional arg0 = {}, std::optional arg1 = {}, std::optional arg2 = {}, std::optional arg3 = {}); void DefineAsExisting(IR::Inst* inst, Argument& arg); void DefineAsRegister(IR::Inst* inst, oaknut::Reg reg);