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Arm: BLX is UNPREDICTABLE when Rm is PC

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This commit is contained in:
MerryMage 2016-08-07 20:50:33 +01:00
parent 1af5bef32c
commit 4dcd1d1859
2 changed files with 4 additions and 1 deletions
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2
src/frontend/translate/translate_arm/branch.cpp
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@ -44,6 +44,8 @@ bool ArmTranslatorVisitor::arm_BLX_imm(bool H, Imm24 imm24) {
} }
bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) { bool ArmTranslatorVisitor::arm_BLX_reg(Cond cond, Reg m) {
if (m == Reg::PC)
return UnpredictableInstruction();
// BLX <Rm> // BLX <Rm>
if (ConditionPassed(cond)) { if (ConditionPassed(cond)) {
ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4)); ir.SetRegister(Reg::LR, ir.Imm32(ir.current_location.PC() + 4));

3
tests/arm/fuzz_arm.cpp
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@ -563,7 +563,8 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
TEST_CASE("Fuzz ARM branch instructions", "[JitX64]") { TEST_CASE("Fuzz ARM branch instructions", "[JitX64]") {
const std::array<InstructionGenerator, 6> instructions = {{ const std::array<InstructionGenerator, 6> instructions = {{
InstructionGenerator("1111101hvvvvvvvvvvvvvvvvvvvvvvvv"), InstructionGenerator("1111101hvvvvvvvvvvvvvvvvvvvvvvvv"),
InstructionGenerator("cccc000100101111111111110011mmmm"), InstructionGenerator("cccc000100101111111111110011mmmm",
[](u32 instr) { return Bits<0, 3>(instr) != 0b1111; }), // R15 is UNPREDICTABLE
InstructionGenerator("cccc1010vvvvvvvvvvvvvvvvvvvvvvvv"), InstructionGenerator("cccc1010vvvvvvvvvvvvvvvvvvvvvvvv"),
InstructionGenerator("cccc1011vvvvvvvvvvvvvvvvvvvvvvvv"), InstructionGenerator("cccc1011vvvvvvvvvvvvvvvvvvvvvvvv"),
InstructionGenerator("cccc000100101111111111110001mmmm"), InstructionGenerator("cccc000100101111111111110001mmmm"),