suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

data_processing_register: Clean-up

Browse source
This commit is contained in:
MerryMage 2018-01-22 22:40:00 +00:00
parent ae5dbcbed6
commit 4c4efb2213
3 changed files with 40 additions and 33 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

56
src/frontend/A64/translate/impl/data_processing_register.cpp
View file

@ -9,54 +9,46 @@
namespace Dynarmic {
namespace A64 {
bool TranslatorVisitor::REV(bool sf, bool opc_0, Reg Rn, Reg Rd)
{
bool TranslatorVisitor::REV(bool sf, bool opc_0, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
if (!sf && opc_0) return UnallocatedEncoding();
size_t datasize = sf ? 64 : 32;
IR::U32U64 operand = X(datasize, Rn);
IR::U32U64 result;
const IR::U32U64 operand = X(datasize, Rn);
if (sf) {
result = ir.ByteReverseDual(operand);
X(datasize, Rd, ir.ByteReverseDual(operand));
} else {
result = ir.ByteReverseWord(operand);
X(datasize, Rd, ir.ByteReverseWord(operand));
}
X(datasize, Rd, result);
return true;
}
bool TranslatorVisitor::REV32_int(Reg Rn, Reg Rd)
{
IR::U64 operand = ir.GetX(Rn);
IR::U32 lo = ir.ByteReverseWord(ir.LeastSignificantWord(operand));
IR::U32 hi = ir.ByteReverseWord(ir.MostSignificantWord(operand).result);
IR::U64 result = ir.Pack2x32To1x64(lo, hi);
bool TranslatorVisitor::REV32_int(Reg Rn, Reg Rd) {
const IR::U64 operand = ir.GetX(Rn);
const IR::U32 lo = ir.ByteReverseWord(ir.LeastSignificantWord(operand));
const IR::U32 hi = ir.ByteReverseWord(ir.MostSignificantWord(operand).result);
const IR::U64 result = ir.Pack2x32To1x64(lo, hi);
X(64, Rd, result);
return true;
}
bool TranslatorVisitor::REV16_int(bool sf, Reg Rn, Reg Rd)
{
size_t datasize = sf ? 64 : 32;
IR::U32U64 operand = X(datasize, Rn);
IR::U32U64 result;
IR::U32U64 hihalf;
IR::U32U64 lohalf;
bool TranslatorVisitor::REV16_int(bool sf, Reg Rn, Reg Rd) {
const size_t datasize = sf ? 64 : 32;
if (sf) {
hihalf = ir.And(ir.LogicalShiftRight(IR::U64(operand), ir.Imm8(8)), ir.Imm64(0x00FF00FF00FF00FF));
lohalf = ir.And(ir.LogicalShiftLeft(IR::U64(operand), ir.Imm8(8)), ir.Imm64(0xFF00FF00FF00FF00));
} else {
hihalf = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0x00FF00FF));
lohalf = ir.And(ir.LogicalShiftLeft(operand, ir.Imm8(8), ir.Imm1(0)).result, ir.Imm32(0xFF00FF00));
}
result = ir.Or(hihalf, lohalf);
const IR::U64 operand = X(datasize, Rn);
const IR::U64 hihalf = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(8)), ir.Imm64(0x00FF00FF00FF00FF));
const IR::U64 lohalf = ir.And(ir.LogicalShiftLeft(operand, ir.Imm8(8)), ir.Imm64(0xFF00FF00FF00FF00));
const IR::U64 result = ir.Or(hihalf, lohalf);
X(datasize, Rd, result);
} else {
const IR::U32 operand = X(datasize, Rn);
const IR::U32 hihalf = ir.And(ir.LogicalShiftRight(operand, ir.Imm8(8)), ir.Imm32(0x00FF00FF));
const IR::U32 lohalf = ir.And(ir.LogicalShiftLeft(operand, ir.Imm8(8)), ir.Imm32(0xFF00FF00));
const IR::U32 result = ir.Or(hihalf, lohalf);
X(datasize, Rd, result);
}
return true;
}

12
src/frontend/ir/ir_emitter.cpp
View file

@ -142,6 +142,18 @@ ResultAndCarry<U32> IREmitter::RotateRightExtended(const U32& value_in, const U1
return {result, carry_out};
}
U32 IREmitter::LogicalShiftLeft(const U32& value_in, const U8& shift_amount) {
return Inst<U32>(Opcode::LogicalShiftLeft32, value_in, shift_amount, Imm1(0));
}
U64 IREmitter::LogicalShiftLeft(const U64& value_in, const U8& shift_amount) {
return Inst<U64>(Opcode::LogicalShiftLeft64, value_in, shift_amount);
}
U32 IREmitter::LogicalShiftRight(const U32& value_in, const U8& shift_amount) {
return Inst<U32>(Opcode::LogicalShiftRight32, value_in, shift_amount, Imm1(0));
}
U64 IREmitter::LogicalShiftRight(const U64& value_in, const U8& shift_amount) {
return Inst<U64>(Opcode::LogicalShiftRight64, value_in, shift_amount);
}

5
src/frontend/ir/ir_emitter.h
View file

@ -94,8 +94,11 @@ public:
ResultAndCarry<U32> LogicalShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in);
ResultAndCarry<U32> ArithmeticShiftRight(const U32& value_in, const U8& shift_amount, const U1& carry_in);
ResultAndCarry<U32> RotateRight(const U32& value_in, const U8& shift_amount, const U1& carry_in);
U64 LogicalShiftRight(const U64& value_in, const U8& shift_amount);
U32 LogicalShiftLeft(const U32& value_in, const U8& shift_amount);
U64 LogicalShiftLeft(const U64& value_in, const U8& shift_amount);
U32U64 LogicalShiftLeft(const U32U64& value_in, const U8& shift_amount);
U32 LogicalShiftRight(const U32& value_in, const U8& shift_amount);
U64 LogicalShiftRight(const U64& value_in, const U8& shift_amount);
U32U64 LogicalShiftRight(const U32U64& value_in, const U8& shift_amount);
U32U64 ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount);
U32U64 RotateRight(const U32U64& value_in, const U8& shift_amount);