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A32: Implement ASIMD VSHLL

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This commit is contained in:
MerryMage 2020-06-24 23:07:49 +01:00
parent ed48a9d7d5
commit 495f58eed8
4 changed files with 39 additions and 2 deletions
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4
src/frontend/A32/decoder/asimd.inc
View file

@ -93,7 +93,7 @@ INST(asimd_VQSHRUN, "VQSHRUN", "111100111Diiiiiidddd100
INST(asimd_VQRSHRUN, "VQRSHRUN", "111100111Diiiiiidddd100001M1mmmm") // ASIMD
INST(asimd_VQSHRN, "VQSHRN", "1111001U1Diiiiiidddd100100M1mmmm") // ASIMD
INST(asimd_VQRSHRN, "VQRSHRN", "1111001U1Diiiiiidddd100101M1mmmm") // ASIMD
//INST(asimd_SHLL, "SHLL", "1111001U1-vvv-------101000-1----") // ASIMD
INST(asimd_VSHLL, "VSHLL", "1111001U1Diiiiiidddd101000M1mmmm") // ASIMD
INST(asimd_VCVT_fixed, "VCVT (fixed-point)", "1111001U1Diiiiiidddd111o0QM1mmmm") // ASIMD
// Two registers, miscellaneous
@ -124,7 +124,7 @@ INST(asimd_VZIP, "VZIP", "111100111D11zz10dddd000
INST(asimd_VMOVN, "VMOVN", "111100111D11zz10dddd001000M0mmmm") // ASIMD
INST(asimd_VQMOVUN, "VQMOVUN", "111100111D11zz10dddd001001M0mmmm") // ASIMD
INST(asimd_VQMOVN, "VQMOVN", "111100111D11zz10dddd00101oM0mmmm") // ASIMD
//INST(asimd_VSHLL_max, "VSHLL_max", "111100111-11--10----001100-0----") // ASIMD
INST(asimd_VSHLL_max, "VSHLL_max", "111100111D11zz10dddd001100M0mmmm") // ASIMD
//INST(asimd_VCVT_half, "VCVT (half-precision)", "111100111-11--10----011x00-0----") // ASIMD
INST(asimd_VRECPE, "VRECPE", "111100111D11zz11dddd010F0QM0mmmm") // ASIMD
INST(asimd_VRSQRTE, "VRSQRTE", "111100111D11zz11dddd010F1QM0mmmm") // ASIMD

15
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View file

@ -595,6 +595,21 @@ bool ArmTranslatorVisitor::asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, b
return true;
}
bool ArmTranslatorVisitor::asimd_VSHLL_max(bool D, size_t sz, size_t Vd, bool M, size_t Vm) {
if (sz == 0b11 || Common::Bit<0>(Vd)) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(true, Vd, D);
const auto m = ToVector(false, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = ir.VectorLogicalShiftLeft(2 * esize, ir.VectorZeroExtend(esize, reg_m), static_cast<u8>(esize));
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();

20
src/frontend/A32/translate/impl/asimd_two_regs_shift.cpp
View file

@ -306,6 +306,26 @@ bool ArmTranslatorVisitor::asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd,
Rounding::Round, U ? Narrowing::SaturateToUnsigned : Narrowing::SaturateToSigned, U ? Signedness::Unsigned : Signedness::Signed);
}
bool ArmTranslatorVisitor::asimd_VSHLL(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm) {
ASSERT_MSG((Common::Bits<3, 5>(imm6) != 0), "Decode error");
if (Common::Bit<0>(Vd)) {
return UndefinedInstruction();
}
const auto [esize, shift_amount] = ElementSizeAndShiftAmount(false, false, imm6);
const auto d = ToVector(true, Vd, D);
const auto m = ToVector(false, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto ext_vec = U ? ir.VectorZeroExtend(esize, reg_m) : ir.VectorSignExtend(esize, reg_m);
const auto result = ir.VectorLogicalShiftLeft(esize * 2, ext_vec, static_cast<u8>(shift_amount));
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, bool to_fixed, bool Q, bool M, size_t Vm) {
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();

2
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -530,6 +530,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VQRSHRUN(bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VQRSHRN(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VSHLL(bool U, bool D, size_t imm6, size_t Vd, bool M, size_t Vm);
bool asimd_VCVT_fixed(bool U, bool D, size_t imm6, size_t Vd, bool to_fixed, bool Q, bool M, size_t Vm);
// Advanced SIMD two register, miscellaneous
@ -560,6 +561,7 @@ struct ArmTranslatorVisitor final {
bool asimd_VMOVN(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
bool asimd_VQMOVUN(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
bool asimd_VQMOVN(bool D, size_t sz, size_t Vd, bool op, bool M, size_t Vm);
bool asimd_VSHLL_max(bool D, size_t sz, size_t Vd, bool M, size_t Vm);
bool asimd_VRECPE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VRSQRTE(bool D, size_t sz, size_t Vd, bool F, bool Q, bool M, size_t Vm);
bool asimd_VCVT_integer(bool D, size_t sz, size_t Vd, bool op, bool U, bool Q, bool M, size_t Vm);