From 48df9b9a7d9ff7291d6446878477a3ab9cf17c91 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Tue, 18 Sep 2018 18:55:15 -0400 Subject: [PATCH] A64: Implement UQSHL's vector immediate and register variants --- src/frontend/A64/decoder/a64.inc | 4 +- .../impl/simd_shift_by_immediate.cpp | 42 ++++++++++++------- .../A64/translate/impl/simd_three_same.cpp | 40 ++++++++++++------ 3 files changed, 57 insertions(+), 29 deletions(-) diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 02b3e640..090ea301 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -750,7 +750,7 @@ INST(UQSUB_2, "UQSUB", "0Q101 INST(CMHI_2, "CMHI (register)", "0Q101110zz1mmmmm001101nnnnnddddd") INST(CMHS_2, "CMHS (register)", "0Q101110zz1mmmmm001111nnnnnddddd") INST(USHL_2, "USHL", "0Q101110zz1mmmmm010001nnnnnddddd") -//INST(UQSHL_reg_2, "UQSHL (register)", "0Q101110zz1mmmmm010011nnnnnddddd") +INST(UQSHL_reg_2, "UQSHL (register)", "0Q101110zz1mmmmm010011nnnnnddddd") INST(URSHL_2, "URSHL", "0Q101110zz1mmmmm010101nnnnnddddd") //INST(UQRSHL_2, "UQRSHL", "0Q101110zz1mmmmm010111nnnnnddddd") INST(UMAX, "UMAX", "0Q101110zz1mmmmm011001nnnnnddddd") @@ -810,7 +810,7 @@ INST(URSRA_2, "URSRA", "0Q101 INST(SRI_2, "SRI", "0Q1011110IIIIiii010001nnnnnddddd") INST(SLI_2, "SLI", "0Q1011110IIIIiii010101nnnnnddddd") //INST(SQSHLU_2, "SQSHLU", "0Q1011110IIIIiii011001nnnnnddddd") -//INST(UQSHL_imm_2, "UQSHL (immediate)", "0Q1011110IIIIiii011101nnnnnddddd") +INST(UQSHL_imm_2, "UQSHL (immediate)", "0Q1011110IIIIiii011101nnnnnddddd") INST(SQSHRUN_2, "SQSHRUN, SQSHRUN2", "0Q1011110IIIIiii100001nnnnnddddd") INST(SQRSHRUN_2, "SQRSHRUN, SQRSHRUN2", "0Q1011110IIIIiii100011nnnnnddddd") INST(UQSHRN_2, "UQSHRN, UQSHRN2", "0Q1011110IIIIiii100101nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp index d5df2cd0..ca5dc019 100644 --- a/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp +++ b/src/frontend/A64/translate/impl/simd_shift_by_immediate.cpp @@ -153,6 +153,29 @@ bool ShiftLeftLong(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec V v.V(2 * datasize, Vd, result); return true; } + +bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd, Signedness sign) { + if (!Q && immh.Bit<3>()) { + return v.ReservedValue(); + } + + const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); + const size_t datasize = Q ? 128 : 64; + const size_t shift = concatenate(immh, immb).ZeroExtend() - esize; + + const IR::U128 operand = v.V(datasize, Vn); + const IR::U128 shift_vec = v.ir.VectorBroadcast(esize, v.I(esize, shift)); + const IR::U128 result = [&] { + if (sign == Signedness::Signed) { + return v.ir.VectorSignedSaturatedShiftLeft(esize, operand, shift_vec); + } + + return v.ir.VectorUnsignedSaturatedShiftLeft(esize, operand, shift_vec); + }(); + + v.V(datasize, Vd, result); + return true; +} } // Anonymous namespace bool TranslatorVisitor::SSHR_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { @@ -199,20 +222,7 @@ bool TranslatorVisitor::RSHRN(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) } bool TranslatorVisitor::SQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { - if (!Q && immh.Bit<3>()) { - return ReservedValue(); - } - - const size_t esize = 8 << Common::HighestSetBit(immh.ZeroExtend()); - const size_t datasize = Q ? 128 : 64; - const size_t shift = concatenate(immh, immb).ZeroExtend() - esize; - - const IR::U128 operand = V(datasize, Vn); - const IR::U128 shift_vec = ir.VectorBroadcast(esize, I(esize, shift)); - const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand, shift_vec); - - V(datasize, Vd, result); - return true; + return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::SQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { @@ -231,6 +241,10 @@ bool TranslatorVisitor::SQRSHRUN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::Round, Narrowing::SaturateToUnsigned, Signedness::Signed); } +bool TranslatorVisitor::UQSHL_imm_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { + return SaturatingShiftLeft(*this, Q, immh, immb, Vn, Vd, Signedness::Unsigned); +} + bool TranslatorVisitor::UQSHRN_2(bool Q, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) { return ShiftRightNarrowing(*this, Q, immh, immb, Vn, Vd, Rounding::None, Narrowing::SaturateToUnsigned, Signedness::Unsigned); } diff --git a/src/frontend/A64/translate/impl/simd_three_same.cpp b/src/frontend/A64/translate/impl/simd_three_same.cpp index 1f560c6f..486b292c 100644 --- a/src/frontend/A64/translate/impl/simd_three_same.cpp +++ b/src/frontend/A64/translate/impl/simd_three_same.cpp @@ -369,6 +369,28 @@ bool SaturatingArithmeticOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Ve return true; } +bool SaturatingShiftLeft(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd, Signedness sign) { + if (size == 0b11 && !Q) { + return v.ReservedValue(); + } + + const size_t esize = 8 << size.ZeroExtend(); + const size_t datasize = Q ? 128 : 64; + + const IR::U128 operand1 = v.V(datasize, Vn); + const IR::U128 operand2 = v.V(datasize, Vm); + const IR::U128 result = [&] { + if (sign == Signedness::Signed) { + return v.ir.VectorSignedSaturatedShiftLeft(esize, operand1, operand2); + } + + return v.ir.VectorUnsignedSaturatedShiftLeft(esize, operand1, operand2); + }(); + + v.V(datasize, Vd, result); + return true; +} + } // Anonymous namespace bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -779,19 +801,7 @@ bool TranslatorVisitor::CMTST_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { } bool TranslatorVisitor::SQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { - if (size == 0b11 && !Q) { - return ReservedValue(); - } - - const size_t esize = 8 << size.ZeroExtend(); - const size_t datasize = Q ? 128 : 64; - - const IR::U128 operand1 = V(datasize, Vn); - const IR::U128 operand2 = V(datasize, Vm); - const IR::U128 result = ir.VectorSignedSaturatedShiftLeft(esize, operand1, operand2); - - V(datasize, Vd, result); - return true; + return SaturatingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Signed); } bool TranslatorVisitor::SRSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { @@ -812,6 +822,10 @@ bool TranslatorVisitor::SSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::UQSHL_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { + return SaturatingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Unsigned); +} + bool TranslatorVisitor::URSHL_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { return RoundingShiftLeft(*this, Q, size, Vm, Vn, Vd, Signedness::Unsigned); }