suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

Add min/max

Browse source
This commit is contained in:
Liam 2022-11-13 19:20:55 -05:00
parent 18e00f2e58
commit 48b0f6369b
1 changed files with 54 additions and 40 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

94
src/dynarmic/backend/arm64/emit_arm64_data_processing.cpp
View file

@ -1423,82 +1423,96 @@ void EmitIR<IR::Opcode::ExtractRegister64>(oaknut::CodeGenerator& code, EmitCont
template<> template<>
void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::ReplicateBit32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; ASSERT(args[1].IsImmediate());
(void)inst;
ASSERT_FALSE("Unimplemented"); auto Wresult = ctx.reg_alloc.WriteW(inst);
auto Wvalue = ctx.reg_alloc.ReadW(args[0]);
const u8 bit = args[1].GetImmediateU8();
RegAlloc::Realize(Wresult, Wvalue);
code.UBFX(Wscratch0, Wvalue, bit, 1);
code.SUB(Wresult, WZR, Wscratch0);
} }
template<> template<>
void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::ReplicateBit64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; auto args = ctx.reg_alloc.GetArgumentInfo(inst);
(void)ctx; ASSERT(args[1].IsImmediate());
(void)inst;
ASSERT_FALSE("Unimplemented"); auto Xresult = ctx.reg_alloc.WriteX(inst);
auto Xvalue = ctx.reg_alloc.ReadX(args[0]);
const u8 bit = args[1].GetImmediateU8();
RegAlloc::Realize(Xresult, Xvalue);
code.UBFX(Xscratch0, Xvalue, bit, 1);
code.SUB(Xresult, XZR, Xscratch0);
}
static void EmitMaxMin32(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, oaknut::Cond cond) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wresult = ctx.reg_alloc.WriteW(inst);
auto Wop1 = ctx.reg_alloc.ReadW(args[0]);
auto Wop2 = ctx.reg_alloc.ReadW(args[1]);
RegAlloc::Realize(Wresult, Wop1, Wop2);
ctx.reg_alloc.SpillFlags();
code.CMP(Wop1->toW(), Wop2);
code.CSEL(Wresult, Wop1, Wop2, cond);
}
static void EmitMaxMin64(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst, oaknut::Cond cond) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Xresult = ctx.reg_alloc.WriteX(inst);
auto Xop1 = ctx.reg_alloc.ReadX(args[0]);
auto Xop2 = ctx.reg_alloc.ReadX(args[1]);
RegAlloc::Realize(Xresult, Xop1, Xop2);
ctx.reg_alloc.SpillFlags();
code.CMP(Xop1->toX(), Xop2);
code.CSEL(Xresult, Xop1, Xop2, cond);
} }
template<> template<>
void EmitIR<IR::Opcode::MaxSigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MaxSigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin32(code, ctx, inst, GT);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MaxSigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MaxSigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin64(code, ctx, inst, GT);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MaxUnsigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MaxUnsigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin32(code, ctx, inst, HI);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MaxUnsigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MaxUnsigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin64(code, ctx, inst, HI);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MinSigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MinSigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin32(code, ctx, inst, LT);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MinSigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MinSigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin64(code, ctx, inst, LT);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MinUnsigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MinUnsigned32>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin32(code, ctx, inst, LO);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
template<> template<>
void EmitIR<IR::Opcode::MinUnsigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) { void EmitIR<IR::Opcode::MinUnsigned64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code; EmitMaxMin64(code, ctx, inst, LO);
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
} }
} // namespace Dynarmic::Backend::Arm64 } // namespace Dynarmic::Backend::Arm64