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backend/rv64: Implement basic LogicalShiftRight32

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Yang Liu 2024-02-19 13:59:23 +08:00 committed by Merry
parent 02d8a7ff10
commit 483dcba9b6
1 changed files with 21 additions and 2 deletions
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23
src/dynarmic/backend/riscv64/emit_riscv64_data_processing.cpp
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@ -125,8 +125,27 @@ void EmitIR<IR::Opcode::LogicalShiftLeft64>(biscuit::Assembler&, EmitContext&, I
} }
template<> template<>
void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler&, EmitContext&, IR::Inst*) { void EmitIR<IR::Opcode::LogicalShiftRight32>(biscuit::Assembler& as, EmitContext& ctx, IR::Inst* inst) {
UNIMPLEMENTED(); const auto carry_inst = inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp);
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto& operand_arg = args[0];
auto& shift_arg = args[1];
// TODO: Add full implementation
ASSERT(carry_inst == nullptr);
ASSERT(shift_arg.IsImmediate());
const u8 shift = shift_arg.GetImmediateU8();
auto Xresult = ctx.reg_alloc.WriteX(inst);
auto Xoperand = ctx.reg_alloc.ReadX(operand_arg);
RegAlloc::Realize(Xresult, Xoperand);
if (shift <= 31) {
as.SRLIW(Xresult, Xoperand, shift);
} else {
as.MV(Xresult, biscuit::zero);
}
} }
template<> template<>