Implement thumb1_RSB_imm

This commit is contained in:
MerryMage 2016-07-10 08:44:07 +08:00
parent 6536ad9618
commit 46408267c3
3 changed files with 18 additions and 2 deletions

View file

@ -56,7 +56,7 @@ private:
};
template <typename V>
static const std::array<Thumb1Matcher<V>, 22> g_thumb1_instruction_table {{
static const std::array<Thumb1Matcher<V>, 23> g_thumb1_instruction_table {{
#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
@ -83,7 +83,7 @@ static const std::array<Thumb1Matcher<V>, 22> g_thumb1_instruction_table {{
{ INST(&V::thumb1_SBC_reg, "SBC (reg)", "0100000110mmmddd") },
{ INST(&V::thumb1_ROR_reg, "ROR (reg)", "0100000111sssddd") },
{ INST(&V::thumb1_TST_reg, "TST (reg)", "0100001000mmmnnn") },
//{ INST(&V::thumb1_NEGS_rr, "NEGS (rr)", "0100001001mmmddd") },
{ INST(&V::thumb1_RSB_imm, "RSB (imm)", "0100001001nnnddd") },
//{ INST(&V::thumb1_CMP_rr, "CMP (rr)", "0100001010mmmnnn") },
//{ INST(&V::thumb1_CMN_rr, "CMN (rr)", "0100001011mmmnnn") },
//{ INST(&V::thumb1_ORRS_rr, "ORRS (rr)", "0100001100mmmddd") },

View file

@ -182,6 +182,11 @@ public:
return Common::StringFromFormat("tst %s, %s", RegStr(n), RegStr(m));
}
std::string thumb1_RSB_imm(Reg n, Reg d) {
// Pre-UAL syntax: NEGS <Rd>, <Rn>
return Common::StringFromFormat("rsbs %s, %s, #0", RegStr(d), RegStr(n));
}
std::string thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m));

View file

@ -258,6 +258,17 @@ struct TranslatorVisitor final {
ir.SetZFlag(ir.IsZero(result));
return true;
}
bool thumb1_RSB_imm(Reg n, Reg d) {
// RSBS <Rd>, <Rn>, #0
// Rd can never encode R15.
auto result = ir.SubWithCarry(ir.Imm32(0), ir.GetRegister(n), ir.Imm1(1));
ir.SetRegister(d, result.result);
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;