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A64: Implement the scalar version of FCVTXN

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Lioncash 2019-03-04 10:58:19 -05:00 committed by MerryMage
parent 7c81a58ed3
commit 4339a8fff6
2 changed files with 13 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -464,7 +464,7 @@ INST(CMLE_1, "CMLE (zero)", "01111
INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd")
INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd")
INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd")
//INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd")
INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Scalar pairwise
INST(ADDP_pair, "ADDP (scalar)", "01011110zz110001101110nnnnnddddd")

12
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
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@ -152,6 +152,18 @@ bool TranslatorVisitor::FCVTPU_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsPlusInfinity, Signedness::Unsigned);
}
bool TranslatorVisitor::FCVTXN_1(bool sz, Vec Vn, Vec Vd) {
if (!sz) {
return UnallocatedEncoding();
}
const IR::U64 element = V_scalar(64, Vn);
const IR::U32 result = ir.FPDoubleToSingle(element, FP::RoundingMode::ToOdd);
V_scalar(32, Vd, result);
return true;
}
bool TranslatorVisitor::FCVTZS_int_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPConvertWithRound(*this, sz, Vn, Vd, FP::RoundingMode::TowardsZero, Signedness::Signed);
}