Merge pull request #586 from lioncash/halfword
thumb32: Implement halfword load instructions
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merry
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41bee2db3c
3 changed files with 157 additions and 14 deletions
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@ -142,6 +142,7 @@ INST(thumb32_STR_reg, "STR (reg)", "111110000100nnnntttt00
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// Load Byte and Memory Hints
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INST(thumb32_PLD_lit, "PLD (lit)", "11111000U00111111111iiiiiiiiiiii")
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INST(thumb32_PLD_lit, "PLD (lit)", "11111000U01111111111iiiiiiiiiiii")
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INST(thumb32_PLD_reg, "PLD (reg)", "1111100000W1nnnn1111000000iimmmm")
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INST(thumb32_PLD_imm8, "PLD (imm8)", "1111100000W1nnnn11111100iiiiiiii")
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INST(thumb32_PLD_imm12, "PLD (imm12)", "1111100010W1nnnn1111iiiiiiiiiiii")
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@ -161,20 +162,20 @@ INST(thumb32_LDRSB_imm8, "LDRSB (imm8)", "111110010001nnnntttt1P
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INST(thumb32_LDRSB_imm12, "LDRSB (imm12)", "111110011001nnnnttttiiiiiiiiiiii")
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// Load Halfword and Memory Hints
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//INST(thumb32_LDRH_lit, "LDRH (lit)", "11111000-0111111----------------")
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//INST(thumb32_LDRH_reg, "LDRH (reg)", "111110000011--------000000------")
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//INST(thumb32_LDRHT, "LDRHT", "111110000011--------1110--------")
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//INST(thumb32_LDRH_imm8, "LDRH (imm8)", "111110000011--------1-----------")
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//INST(thumb32_LDRH_imm12, "LDRH (imm12)", "111110001011--------------------")
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//INST(thumb32_LDRSH_lit, "LDRSH (lit)", "11111001-0111111----------------")
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//INST(thumb32_LDRSH_reg, "LDRSH (reg)", "111110010011--------000000------")
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//INST(thumb32_LDRSHT, "LDRSHT", "111110010011--------1110--------")
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//INST(thumb32_LDRSH_imm8, "LDRSH (imm8)", "111110010011--------1-----------")
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//INST(thumb32_LDRSH_imm12, "LDRSH (imm12)", "111110011011--------------------")
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//INST(thumb32_NOP, "NOP", "111110010011----1111000000------")
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//INST(thumb32_NOP, "NOP", "111110010011----11111100--------")
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//INST(thumb32_NOP, "NOP", "11111001-01111111111------------")
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//INST(thumb32_NOP, "NOP", "111110011011----1111------------")
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INST(thumb32_LDRH_lit, "LDRH (lit)", "11111000U0111111ttttiiiiiiiiiiii")
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INST(thumb32_LDRH_reg, "LDRH (reg)", "111110000011nnnntttt000000iimmmm")
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INST(thumb32_LDRHT, "LDRHT", "111110000011nnnntttt1110iiiiiiii")
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INST(thumb32_LDRH_imm8, "LDRH (imm8)", "111110000011nnnntttt1PUWiiiiiiii")
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INST(thumb32_LDRH_imm12, "LDRH (imm12)", "111110001011nnnnttttiiiiiiiiiiii")
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INST(thumb32_NOP, "NOP", "11111001-01111111111------------")
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INST(thumb32_LDRSH_lit, "LDRSH (lit)", "11111001U0111111ttttiiiiiiiiiiii")
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INST(thumb32_NOP, "NOP", "111110010011----1111000000------")
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INST(thumb32_LDRSH_reg, "LDRSH (reg)", "111110010011nnnntttt000000iimmmm")
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INST(thumb32_LDRSHT, "LDRSHT", "111110010011nnnntttt1110iiiiiiii")
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INST(thumb32_NOP, "NOP", "111110010011----11111100--------")
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INST(thumb32_NOP, "NOP", "111110011011----1111------------")
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INST(thumb32_LDRSH_imm8, "LDRSH (imm8)", "111110010011nnnntttt1PUWiiiiiiii")
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INST(thumb32_LDRSH_imm12, "LDRSH (imm12)", "111110011011nnnnttttiiiiiiiiiiii")
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// Load Word
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INST(thumb32_LDR_lit, "LDR (lit)", "11111000U1011111ttttiiiiiiiiiiii")
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@ -7,5 +7,135 @@
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namespace Dynarmic::A32 {
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using ExtensionFunction = IR::U32 (IREmitter::*)(const IR::U16&);
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static bool LoadHalfLiteral(ThumbTranslatorVisitor& v, bool U, Reg t, Imm<12> imm12,
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ExtensionFunction ext_fn) {
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const auto imm32 = imm12.ZeroExtend();
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const auto base = v.ir.AlignPC(4);
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const auto address = U ? (base + imm32) : (base - imm32);
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const auto data = (v.ir.*ext_fn)(v.ir.ReadMemory16(v.ir.Imm32(address)));
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v.ir.SetRegister(t, data);
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return true;
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}
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static bool LoadHalfRegister(ThumbTranslatorVisitor& v, Reg n, Reg t, Imm<2> imm2, Reg m,
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ExtensionFunction ext_fn) {
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if (m == Reg::PC) {
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return v.UnpredictableInstruction();
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}
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const IR::U32 reg_m = v.ir.GetRegister(m);
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 offset = v.ir.LogicalShiftLeft(reg_m, v.ir.Imm8(imm2.ZeroExtend<u8>()));
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const IR::U32 address = v.ir.Add(reg_n, offset);
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const IR::U32 data = (v.ir.*ext_fn)(v.ir.ReadMemory16(address));
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v.ir.SetRegister(t, data);
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return true;
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}
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static bool LoadHalfImmediate(ThumbTranslatorVisitor& v, Reg n, Reg t, bool P, bool U, bool W,
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Imm<12> imm12, ExtensionFunction ext_fn) {
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const u32 imm32 = imm12.ZeroExtend();
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const IR::U32 reg_n = v.ir.GetRegister(n);
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const IR::U32 offset_address = U ? v.ir.Add(reg_n, v.ir.Imm32(imm32))
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: v.ir.Sub(reg_n, v.ir.Imm32(imm32));
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const IR::U32 address = P ? offset_address
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: reg_n;
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const IR::U32 data = (v.ir.*ext_fn)(v.ir.ReadMemory16(address));
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if (W) {
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v.ir.SetRegister(n, offset_address);
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}
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v.ir.SetRegister(t, data);
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_LDRH_lit(bool U, Reg t, Imm<12> imm12) {
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return LoadHalfLiteral(*this, U, t, imm12, &IREmitter::ZeroExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRH_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return LoadHalfRegister(*this, n, t, imm2, m, &IREmitter::ZeroExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRH_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
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if (!P && !W) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC && W) {
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return UnpredictableInstruction();
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}
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if (W && n == t) {
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return UnpredictableInstruction();
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}
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return LoadHalfImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
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&IREmitter::ZeroExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRH_imm12(Reg n, Reg t, Imm<12> imm12) {
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return LoadHalfImmediate(*this, n, t, true, true, false, imm12,
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&IREmitter::ZeroExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRHT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution levels.
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat it as a normal LDRH, given we don't support
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// execution levels other than EL0 currently.
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return thumb32_LDRH_imm8(n, t, true, true, false, imm8);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSH_lit(bool U, Reg t, Imm<12> imm12) {
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return LoadHalfLiteral(*this, U, t, imm12, &IREmitter::SignExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSH_reg(Reg n, Reg t, Imm<2> imm2, Reg m) {
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return LoadHalfRegister(*this, n, t, imm2, m, &IREmitter::SignExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSH_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8) {
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if (!P && !W) {
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return UndefinedInstruction();
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}
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if (t == Reg::PC && W) {
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return UnpredictableInstruction();
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}
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if (W && n == t) {
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return UnpredictableInstruction();
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}
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return LoadHalfImmediate(*this, n, t, P, U, W, Imm<12>{imm8.ZeroExtend()},
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&IREmitter::SignExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSH_imm12(Reg n, Reg t, Imm<12> imm12) {
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return LoadHalfImmediate(*this, n, t, true, true, false, imm12,
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&IREmitter::SignExtendHalfToWord);
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}
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bool ThumbTranslatorVisitor::thumb32_LDRSHT(Reg n, Reg t, Imm<8> imm8) {
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// TODO: Add an unpredictable instruction path if this
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// is executed in hypervisor mode if we ever support
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// privileged execution levels.
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if (t == Reg::PC) {
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return UnpredictableInstruction();
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}
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// Treat it as a normal LDRSH, given we don't support
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// execution levels other than EL0 currently.
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return thumb32_LDRSH_imm8(n, t, true, true, false, imm8);
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}
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} // namespace Dynarmic::A32
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@ -267,6 +267,18 @@ struct ThumbTranslatorVisitor final {
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bool thumb32_LDRSB_imm12(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_LDRSBT(Reg n, Reg t, Imm<8> imm8);
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// thumb32 load halfword instructions
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bool thumb32_LDRH_lit(bool U, Reg t, Imm<12> imm12);
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bool thumb32_LDRH_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_LDRH_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
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bool thumb32_LDRH_imm12(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_LDRHT(Reg n, Reg t, Imm<8> imm8);
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bool thumb32_LDRSH_lit(bool U, Reg t, Imm<12> imm12);
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bool thumb32_LDRSH_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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bool thumb32_LDRSH_imm8(Reg n, Reg t, bool P, bool U, bool W, Imm<8> imm8);
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bool thumb32_LDRSH_imm12(Reg n, Reg t, Imm<12> imm12);
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bool thumb32_LDRSHT(Reg n, Reg t, Imm<8> imm8);
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// thumb32 load word instructions
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bool thumb32_LDR_lit(bool U, Reg t, Imm<12> imm12);
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bool thumb32_LDR_reg(Reg n, Reg t, Imm<2> imm2, Reg m);
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