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A64: Implement SQXTN, SQXTUN, and UQXTN's scalar variants

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We can implement these in terms of the vector variants
This commit is contained in:
Lioncash 2018-08-19 19:28:03 -04:00 committed by MerryMage
parent 4ff39c6ea8
commit 3d465e2c36
3 changed files with 35 additions and 7 deletions
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6
src/frontend/A64/decoder/a64.inc
View file

@ -412,14 +412,14 @@ INST(CMGT_zero_1, "CMGT (zero)", "01011
INST(CMEQ_zero_1, "CMEQ (zero)", "01011110zz100000100110nnnnnddddd")
INST(CMLT_1, "CMLT (zero)", "01011110zz100000101010nnnnnddddd")
INST(ABS_1, "ABS", "01011110zz100000101110nnnnnddddd")
//INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd")
INST(SQXTN_1, "SQXTN, SQXTN2", "01011110zz100001010010nnnnnddddd")
//INST(USQADD_1, "USQADD", "01111110zz100000001110nnnnnddddd")
//INST(SQNEG_1, "SQNEG", "01111110zz100000011110nnnnnddddd")
INST(CMGE_zero_1, "CMGE (zero)", "01111110zz100000100010nnnnnddddd")
INST(CMLE_1, "CMLE (zero)", "01111110zz100000100110nnnnnddddd")
INST(NEG_1, "NEG (vector)", "01111110zz100000101110nnnnnddddd")
//INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd")
//INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd")
INST(SQXTUN_1, "SQXTUN, SQXTUN2", "01111110zz100001001010nnnnnddddd")
INST(UQXTN_1, "UQXTN, UQXTN2", "01111110zz100001010010nnnnnddddd")
//INST(FCVTXN_1, "FCVTXN, FCVTXN2", "011111100z100001011010nnnnnddddd")
// Data Processing - FP and SIMD - SIMD Scalar pairwise

8
src/frontend/A64/translate/impl/impl.h
View file

@ -522,15 +522,15 @@ struct TranslatorVisitor final {
bool CMEQ_zero_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMLT_1(Imm<2> size, Vec Vn, Vec Vd);
bool ABS_1(Imm<2> size, Vec Vn, Vec Vd);
bool SQXTN_1(Imm<2> size, Vec Vn, Reg Rd);
bool SQXTN_1(Imm<2> size, Vec Vn, Vec Vd);
bool USQADD_1(Imm<2> size, Vec Vn, Vec Vd);
bool SQNEG_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMGE_zero_1(Imm<2> size, Vec Vn, Vec Vd);
bool CMLE_1(Imm<2> size, Vec Vn, Vec Vd);
bool NEG_1(Imm<2> size, Vec Vn, Vec Vd);
bool SQXTUN_1(Imm<2> size, Vec Vn, Reg Rd);
bool UQXTN_1(Imm<2> size, Vec Vn, Reg Rd);
bool FCVTXN_1(bool sz, Vec Vn, Reg Rd);
bool SQXTUN_1(Imm<2> size, Vec Vn, Vec Vd);
bool UQXTN_1(Imm<2> size, Vec Vn, Vec Vd);
bool FCVTXN_1(bool sz, Vec Vn, Vec Vd);
// Data Processing - FP and SIMD - SIMD Scalar pairwise
bool ADDP_pair(Imm<2> size, Vec Vn, Vec Vd);

28
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -73,6 +73,22 @@ bool ScalarFPConvertWithRound(TranslatorVisitor& v, bool sz, Vec Vn, Vec Vd,
v.V_scalar(esize, Vd, result);
return true;
}
using NarrowingFn = IR::U128 (IR::IREmitter::*)(size_t, const IR::U128&);
bool SaturatedNarrow(TranslatorVisitor& v, Imm<2> size, Vec Vn, Vec Vd, NarrowingFn fn) {
if (size == 0b11) {
return v.ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const IR::U128 operand = v.ir.ZeroExtendToQuad(v.V_scalar(2 * esize, Vn));
const IR::U128 result = (v.ir.*fn)(2 * esize, operand);
v.V_scalar(64, Vd, v.ir.VectorGetElement(64, result, 0));
return true;
}
} // Anonymous namespace
bool TranslatorVisitor::ABS_1(Imm<2> size, Vec Vn, Vec Vd) {
@ -193,6 +209,14 @@ bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToSigned);
}
bool TranslatorVisitor::SQXTUN_1(Imm<2> size, Vec Vn, Vec Vd) {
return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorSignedSaturatedNarrowToUnsigned);
}
bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
const auto esize = sz ? 64 : 32;
@ -206,4 +230,8 @@ bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UQXTN_1(Imm<2> size, Vec Vn, Vec Vd) {
return SaturatedNarrow(*this, size, Vn, Vd, &IREmitter::VectorUnsignedSaturatedNarrow);
}
} // namespace Dynarmic::A64