Implement thumb1_SUB_imm
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a2e40eb922
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3 changed files with 18 additions and 2 deletions
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@ -56,7 +56,7 @@ private:
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};
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};
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template <typename V>
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template <typename V>
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static const std::array<Thumb1Matcher<V>, 13> g_thumb1_instruction_table {{
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static const std::array<Thumb1Matcher<V>, 14> g_thumb1_instruction_table {{
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#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
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#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
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@ -67,7 +67,7 @@ static const std::array<Thumb1Matcher<V>, 13> g_thumb1_instruction_table {{
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{ INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") },
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{ INST(&V::thumb1_ADD_reg_t1, "ADD (reg, T1)", "0001100mmmnnnddd") },
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{ INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") },
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{ INST(&V::thumb1_SUB_reg, "SUB (reg)", "0001101mmmnnnddd") },
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{ INST(&V::thumb1_ADD_imm, "ADD (imm)", "0001110vvvnnnddd") },
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{ INST(&V::thumb1_ADD_imm, "ADD (imm)", "0001110vvvnnnddd") },
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//{ INST(&V::thumb1_SUB_rri, "SUB (rri)", "0001111mmmnnnddd") },
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{ INST(&V::thumb1_SUB_imm, "SUB (imm)", "0001111vvvnnnddd") },
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//{ INST(&V::thumb1_MOV_ri, "MOV (ri)", "00100dddvvvvvvvv") },
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//{ INST(&V::thumb1_MOV_ri, "MOV (ri)", "00100dddvvvvvvvv") },
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//{ INST(&V::thumb1_CMP_ri, "CMP (ri)", "00101dddvvvvvvvv") },
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//{ INST(&V::thumb1_CMP_ri, "CMP (ri)", "00101dddvvvvvvvv") },
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//{ INST(&V::thumb1_ADD_ri, "ADD (ri)", "00110dddvvvvvvvv") },
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//{ INST(&V::thumb1_ADD_ri, "ADD (ri)", "00110dddvvvvvvvv") },
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@ -126,6 +126,10 @@ public:
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return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
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return Common::StringFromFormat("adds %s, %s, #%u", RegStr(d), RegStr(n), imm3);
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}
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}
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std::string thumb1_SUB_imm(Imm3 imm3, Reg n, Reg d) {
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return Common::StringFromFormat("subs %s, %s, #%u", RegStr(d), RegStr(n), imm3);
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}
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std::string thumb1_AND_reg(Reg m, Reg d_n) {
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std::string thumb1_AND_reg(Reg m, Reg d_n) {
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return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
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return Common::StringFromFormat("ands %s, %s", RegStr(d_n), RegStr(m));
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}
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}
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@ -98,6 +98,18 @@ struct TranslatorVisitor final {
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ir.SetVFlag(result.overflow);
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ir.SetVFlag(result.overflow);
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return true;
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return true;
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}
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}
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bool thumb1_SUB_imm(Imm3 imm3, Reg n, Reg d) {
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u32 imm32 = imm3 & 0x7;
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// SUBS <Rd>, <Rn>, #<imm3>
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// Rd can never encode R15.
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auto result = ir.SubWithCarry(ir.GetRegister(n), ir.Imm32(imm32), ir.Imm1(1));
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ir.SetRegister(d, result.result);
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ir.SetNFlag(ir.MostSignificantBit(result.result));
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ir.SetZFlag(ir.IsZero(result.result));
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ir.SetCFlag(result.carry);
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ir.SetVFlag(result.overflow);
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return true;
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}
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bool thumb1_AND_reg(Reg m, Reg d_n) {
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bool thumb1_AND_reg(Reg m, Reg d_n) {
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const Reg d = d_n, n = d_n;
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const Reg d = d_n, n = d_n;
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