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emit_arm64_a32: Implement A32SetCpsrNZCVRaw, A32SetCpsrNZCVQ

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Merry 2022-07-30 19:10:35 +01:00 committed by merry
parent 11b665c027
commit 33b3376fb1
1 changed files with 14 additions and 8 deletions
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22
src/dynarmic/backend/arm64/emit_arm64_a32.cpp
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@ -274,18 +274,24 @@ void EmitIR<IR::Opcode::A32SetCpsrNZCV>(oaknut::CodeGenerator& code, EmitContext
template<>
void EmitIR<IR::Opcode::A32SetCpsrNZCVRaw>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code;
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wnzcv = ctx.reg_alloc.ReadW(args[0]);
RegAlloc::Realize(Wnzcv);
code.STR(Wnzcv, Xstate, offsetof(A32JitState, cpsr_nzcv));
}
template<>
void EmitIR<IR::Opcode::A32SetCpsrNZCVQ>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
(void)code;
(void)ctx;
(void)inst;
ASSERT_FALSE("Unimplemented");
auto args = ctx.reg_alloc.GetArgumentInfo(inst);
auto Wnzcv = ctx.reg_alloc.ReadW(args[0]);
RegAlloc::Realize(Wnzcv);
static_assert(offsetof(A32JitState, cpsr_nzcv) + sizeof(u32) == offsetof(A32JitState, cpsr_q));
code.AND(Wscratch0, Wnzcv, 0xf000'0000);
code.AND(Wscratch1, Wnzcv, 0x0800'0000);
code.STP(Wscratch0, Wscratch1, Xstate, offsetof(A32JitState, cpsr_nzcv));
}
template<>