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TranslateArm: Implement VPUSH and VPOP.

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This commit is contained in:
bunnei 2016-08-13 01:51:55 -04:00 committed by MerryMage
parent 9c82a12f8f
commit 30f3d869cc
6 changed files with 118 additions and 2 deletions
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15
src/frontend/arm_types.h
View file

@ -137,6 +137,21 @@ const char* RegToString(Reg reg);
const char* ExtRegToString(ExtReg reg); const char* ExtRegToString(ExtReg reg);
std::string RegListToString(RegList reg_list); std::string RegListToString(RegList reg_list);
inline size_t RegNumber(Reg reg) {
ASSERT(reg != Reg::INVALID_REG);
return static_cast<size_t>(reg);
}
inline size_t RegNumber(ExtReg reg) {
if (reg >= ExtReg::S0 && reg <= ExtReg::S31) {
return static_cast<size_t>(reg) - static_cast<size_t>(ExtReg::S0);
} else if (reg >= ExtReg::D0 && reg <= ExtReg::D31) {
return static_cast<size_t>(reg) - static_cast<size_t>(ExtReg::D0);
} else {
ASSERT_MSG(false, "Invalid extended register");
}
}
inline Reg operator+(Reg reg, int number) { inline Reg operator+(Reg reg, int number) {
ASSERT(reg != Reg::INVALID_REG); ASSERT(reg != Reg::INVALID_REG);

4
src/frontend/decoder/vfp2.h
View file

@ -89,6 +89,8 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"), INST(&V::vfp2_VABS, "VABS", "cccc11101D110000dddd101z11M0mmmm"),
INST(&V::vfp2_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm"), INST(&V::vfp2_VNEG, "VNEG", "cccc11101D110001dddd101z01M0mmmm"),
INST(&V::vfp2_VSQRT, "VSQRT", "cccc11101D110001dddd101z11M0mmmm"), INST(&V::vfp2_VSQRT, "VSQRT", "cccc11101D110001dddd101z11M0mmmm"),
INST(&V::vfp2_VPUSH, "VPUSH", "cccc11010D101101dddd101zvvvvvvvv"),
INST(&V::vfp2_VPOP, "VPOP", "cccc11001D111101dddd101zvvvvvvvv"),
// VCMP // VCMP
// VCMPE // VCMPE
// VCVT // VCVT
@ -98,12 +100,10 @@ boost::optional<const VFP2Matcher<V>&> DecodeVFP2(u32 instruction) {
// VSTR // VSTR
// VSTM // VSTM
// VSTMDB // VSTMDB
// VPUSH
INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"), INST(&V::vfp2_VLDR, "VLDR", "cccc1101UD01nnnndddd101zvvvvvvvv"),
INST(&V::vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv"), INST(&V::vfp2_VSTR, "VSTR", "cccc1101UD00nnnndddd101zvvvvvvvv"),
// VLDM // VLDM
// VLDMDB // VLDMDB
// VPOP
#undef INST #undef INST

8
src/frontend/disassembler/disassembler_arm.cpp
View file

@ -842,6 +842,14 @@ public:
return Common::StringFromFormat("vsqrt%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str()); return Common::StringFromFormat("vsqrt%s.%s %s, %s", CondToString(cond), sz ? "f64" : "f32", FPRegStr(sz, Vd, D).c_str(), FPRegStr(sz, Vm, M).c_str());
} }
std::string vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
return Common::StringFromFormat("vpop%s %s(+%u)", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), imm8 >> (sz ? 1 : 0));
}
std::string vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
return Common::StringFromFormat("vpush%s %s(+%u)", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), imm8 >> (sz ? 1 : 0));
}
std::string vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) { std::string vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2; u32 imm32 = imm8 << 2;
return Common::StringFromFormat("vldr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32); return Common::StringFromFormat("vldr%s %s, [%s, #%c%u]", CondToString(cond), FPRegStr(sz, Vd, D).c_str(), RegToString(n), U ? '+' : '-', imm32);

2
src/frontend/translate/translate_arm/translate_arm.h
View file

@ -350,6 +350,8 @@ struct ArmTranslatorVisitor final {
bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp2_VABS(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp2_VNEG(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm); bool vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, bool M, size_t Vm);
bool vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
bool vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8);
// Floating-point load-store instructions // Floating-point load-store instructions
bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8); bool vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8);

67
src/frontend/translate/translate_arm/vfp2.cpp
View file

@ -360,6 +360,73 @@ bool ArmTranslatorVisitor::vfp2_VSQRT(Cond cond, bool D, size_t Vd, bool sz, boo
return true; return true;
} }
bool ArmTranslatorVisitor::vfp2_VPOP(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
const ExtReg d = ToExtReg(sz, Vd, D);
const unsigned regs = sz ? imm8 >> 1 : imm8;
if (regs == 0 || RegNumber(d)+regs > 32)
return UnpredictableInstruction();
if (sz && regs > 16)
return UnpredictableInstruction();
// VPOP.{F32,F64} <list>
if (ConditionPassed(cond)) {
auto address = ir.GetRegister(Reg::SP);
for (unsigned i = 0; i < regs; ++i) {
if (sz) {
auto lo = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));
auto hi = ir.ReadMemory32(address);
address = ir.Add(address, ir.Imm32(4));
if (ir.current_location.EFlag()) std::swap(lo, hi);
ir.SetExtendedRegister(d + i, ir.TransferToFP64(ir.Pack2x32To1x64(lo, hi)));
} else {
auto res = ir.ReadMemory32(address);
ir.SetExtendedRegister(d + i, ir.TransferToFP32(res));
address = ir.Add(address, ir.Imm32(4));
}
}
ir.SetRegister(Reg::SP, address);
}
return true;
}
bool ArmTranslatorVisitor::vfp2_VPUSH(Cond cond, bool D, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2;
const ExtReg d = ToExtReg(sz, Vd, D);
const unsigned regs = sz ? imm8 >> 1 : imm8;
if (regs == 0 || RegNumber(d)+regs > 32)
return UnpredictableInstruction();
if (sz && regs > 16)
return UnpredictableInstruction();
// VPUSH.{F32,F64} <list>
if (ConditionPassed(cond)) {
auto address = ir.Sub(ir.GetRegister(Reg::SP), ir.Imm32(imm32));
ir.SetRegister(Reg::SP, address);
for (unsigned i = 0; i < regs; ++i) {
if (sz) {
const auto d_u64 = ir.TransferFromFP64(ir.GetExtendedRegister(d + i));
auto lo = ir.LeastSignificantWord(d_u64);
auto hi = ir.MostSignificantWord(d_u64).result;
if (ir.current_location.EFlag()) std::swap(lo, hi);
ir.WriteMemory32(address, lo);
address = ir.Add(address, ir.Imm32(4));
ir.WriteMemory32(address, hi);
address = ir.Add(address, ir.Imm32(4));
} else {
ir.WriteMemory32(address, ir.TransferFromFP32(ir.GetExtendedRegister(d + i)));
address = ir.Add(address, ir.Imm32(4));
}
}
}
return true;
}
bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) { bool ArmTranslatorVisitor::vfp2_VLDR(Cond cond, bool U, bool D, Reg n, size_t Vd, bool sz, Imm8 imm8) {
u32 imm32 = imm8 << 2; u32 imm32 = imm8 << 2;
ExtReg d = ToExtReg(sz, Vd, D); ExtReg d = ToExtReg(sz, Vd, D);

24
tests/arm/fuzz_arm.cpp
View file

@ -846,3 +846,27 @@ TEST_CASE("Fuzz ARM parallel instructions", "[JitX64]") {
}); });
} }
} }
TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][vfp]") {
const auto is_valid = [](u32 instr) -> bool {
auto regs = (instr & 0x100) ? (Bits<0, 7>(instr) >> 1) : Bits<0, 7>(instr);
auto base = Bits<12, 15>(instr);
unsigned d;
if (instr & 0x100) {
d = (base + ((instr & 0x400000) ? 16 : 0));
} else {
d = ((base << 1) + ((instr & 0x400000) ? 1 : 0));
}
// if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE
return regs != 0 && regs <= 16 && (d + regs) <= 32;
};
const std::array<InstructionGenerator, 2> instructions = {{
InstructionGenerator("cccc11010D101101dddd101zvvvvvvvv", is_valid), // VPUSH
InstructionGenerator("cccc11001D111101dddd1010vvvvvvvv", is_valid), // VPOP
}};
FuzzJitArm(5, 6, 10000, [&instructions]() -> u32 {
return instructions[RandInt<size_t>(0, instructions.size() - 1)].Generate();
});
}