suyu/dynarmic
26
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement CLS's vector variant

Browse source 
Leverages CLZ like the integral variant does.
This commit is contained in:
Lioncash 2018-09-16 18:41:01 -04:00 committed by MerryMage
parent a2cd643525
commit 2e0fcd6161
2 changed files with 23 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -567,7 +567,7 @@ INST(REV64_asimd, "REV64", "0Q001
INST(REV16_asimd, "REV16 (vector)", "0Q001110zz100000000110nnnnnddddd")
INST(SADDLP, "SADDLP", "0Q001110zz100000001010nnnnnddddd")
INST(SUQADD_2, "SUQADD", "0Q001110zz100000001110nnnnnddddd")
//INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd")
INST(CLS_asimd, "CLS (vector)", "0Q001110zz100000010010nnnnnddddd")
INST(CNT, "CNT", "0Q001110zz100000010110nnnnnddddd")
INST(SADALP, "SADALP", "0Q001110zz100000011010nnnnnddddd")
INST(SQABS_2, "SQABS", "0Q001110zz100000011110nnnnnddddd")

22
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -193,6 +193,28 @@ bool PairedAddLong(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vn, Vec Vd, Si
} // Anonymous namespace
bool TranslatorVisitor::CLS_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 shifted = ir.VectorArithmeticShiftRight(esize, operand, static_cast<u8>(esize));
const IR::U128 xored = ir.VectorEor(operand, shifted);
const IR::U128 clz = ir.VectorCountLeadingZeros(esize, xored);
IR::U128 result = ir.VectorSub(esize, clz, ir.VectorBroadcast(esize, I(esize, 1)));
if (datasize == 64) {
result = ir.VectorZeroUpper(result);
}
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::CLZ_asimd(bool Q, Imm<2> size, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();