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A64: Implement SMAXP, SMINP, UMAXP, UMINP

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Lioncash 2018-07-29 17:35:11 -04:00 committed by MerryMage
parent 463b9a3d02
commit 2bea2d0512
2 changed files with 59 additions and 4 deletions
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8
src/frontend/A64/decoder/a64.inc
View file

@ -720,8 +720,8 @@ INST(ADD_vector, "ADD (vector)", "0Q001
INST(CMTST_2, "CMTST", "0Q001110zz1mmmmm100011nnnnnddddd")
INST(MLA_vec, "MLA (vector)", "0Q001110zz1mmmmm100101nnnnnddddd")
INST(MUL_vec, "MUL (vector)", "0Q001110zz1mmmmm100111nnnnnddddd")
//INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd")
//INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
INST(SMAXP, "SMAXP", "0Q001110zz1mmmmm101001nnnnnddddd")
INST(SMINP, "SMINP", "0Q001110zz1mmmmm101011nnnnnddddd")
//INST(SQDMULH_vec_2, "SQDMULH (vector)", "0Q001110zz1mmmmm101101nnnnnddddd")
INST(ADDP_vec, "ADDP (vector)", "0Q001110zz1mmmmm101111nnnnnddddd")
//INST(FMAXNM_2, "FMAXNM (vector)", "0Q0011100z1mmmmm110001nnnnnddddd")
@ -761,8 +761,8 @@ INST(SUB_2, "SUB (vector)", "0Q101
INST(CMEQ_reg_2, "CMEQ (register)", "0Q101110zz1mmmmm100011nnnnnddddd")
INST(MLS_vec, "MLS (vector)", "0Q101110zz1mmmmm100101nnnnnddddd")
INST(PMUL, "PMUL", "0Q101110zz1mmmmm100111nnnnnddddd")
//INST(UMAXP, "UMAXP", "0Q101110zz1mmmmm101001nnnnnddddd")
//INST(UMINP, "UMINP", "0Q101110zz1mmmmm101011nnnnnddddd")
INST(UMAXP, "UMAXP", "0Q101110zz1mmmmm101001nnnnnddddd")
INST(UMINP, "UMINP", "0Q101110zz1mmmmm101011nnnnnddddd")
//INST(SQRDMULH_vec_2, "SQRDMULH (vector)", "0Q101110zz1mmmmm101101nnnnnddddd")
//INST(FMAXNMP_vec_2, "FMAXNMP (vector)", "0Q1011100z1mmmmm110001nnnnnddddd")
//INST(FMLAL_vec_2, "FMLAL, FMLAL2 (vector)", "0Q1011100z1mmmmm110011nnnnnddddd")

55
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -173,6 +173,45 @@ bool FPMinMaxOperation(TranslatorVisitor& v, bool Q, bool sz, Vec Vm, Vec Vn, Ve
return true;
}
bool PairedMinMaxOperation(TranslatorVisitor& v, bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd,
MinMaxOperation operation, Signedness sign) {
if (size == 0b11) {
return v.ReservedValue();
}
const size_t esize = 8 << size.ZeroExtend();
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand1 = v.V(datasize, Vn);
const IR::U128 operand2 = v.V(datasize, Vm);
IR::U128 result = [&] {
switch (operation) {
case MinMaxOperation::Max:
if (sign == Signedness::Signed) {
return v.ir.VectorPairedMaxSigned(esize, operand1, operand2);
}
return v.ir.VectorPairedMaxUnsigned(esize, operand1, operand2);
case MinMaxOperation::Min:
if (sign == Signedness::Signed) {
return v.ir.VectorPairedMinSigned(esize, operand1, operand2);
}
return v.ir.VectorPairedMinUnsigned(esize, operand1, operand2);
default:
UNREACHABLE();
return IR::U128{};
}
}();
if (datasize == 64) {
result = v.ir.VectorShuffleWords(result, 0b11101000);
}
v.V(datasize, Vd, result);
return true;
}
} // Anonymous namespace
bool TranslatorVisitor::CMGT_reg_2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
@ -224,6 +263,10 @@ bool TranslatorVisitor::SMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Max, Signedness::Signed);
}
bool TranslatorVisitor::SMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
@ -238,6 +281,10 @@ bool TranslatorVisitor::SMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Signed);
}
bool TranslatorVisitor::ADD_vector(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11 && !Q) return ReservedValue();
const size_t esize = 8 << size.ZeroExtend<size_t>();
@ -587,6 +634,10 @@ bool TranslatorVisitor::UMAX(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UMAXP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Max, Signedness::Unsigned);
}
bool TranslatorVisitor::UABA(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
if (size == 0b11) {
return ReservedValue();
@ -636,6 +687,10 @@ bool TranslatorVisitor::UMIN(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::UMINP(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) {
return PairedMinMaxOperation(*this, Q, size, Vm, Vn, Vd, MinMaxOperation::Min, Signedness::Unsigned);
}
bool TranslatorVisitor::FSUB_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
if (sz && !Q) {
return ReservedValue();