A32: Implement ARM-mode BFI
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fab3a59e05
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2970b34e3c
5 changed files with 32 additions and 3 deletions
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@ -165,6 +165,7 @@ INST(arm_STM_usr, "STM (usr reg)", "----100--100--------------------
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// Miscellaneous instructions
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INST(arm_BFC, "BFC", "cccc0111110vvvvvddddvvvvv0011111") // v6T2
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INST(arm_BFI, "BFI", "cccc0111110vvvvvddddvvvvv001nnnn") // v6T2
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INST(arm_CLZ, "CLZ", "cccc000101101111dddd11110001mmmm") // v5
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INST(arm_NOP, "NOP", "----0011001000001111000000000000") // v6K
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INST(arm_SEL, "SEL", "cccc01101000nnnndddd11111011mmmm") // v6
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@ -586,6 +586,9 @@ public:
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std::string arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
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return fmt::format("bfc{} {}, #{}, #{}", CondToString(cond), d, lsb, msb - lsb + 1);
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}
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std::string arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
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return fmt::format("bfi{} {}, {}, #{}, #{}", CondToString(cond), d, n, lsb, msb - lsb + 1);
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}
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std::string arm_CLZ(Cond cond, Reg d, Reg m) {
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return fmt::format("clz{} {}, {}", CondToString(cond), d, m);
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}
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@ -30,6 +30,29 @@ bool ArmTranslatorVisitor::arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb) {
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return true;
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}
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// BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
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bool ArmTranslatorVisitor::arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n) {
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if (d == Reg::PC) {
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return UnpredictableInstruction();
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}
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if (msb < lsb) {
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return UnpredictableInstruction();
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}
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if (!ConditionPassed(cond)) {
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return true;
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}
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const u32 inclusion_mask = Common::Ones<u32>(msb - lsb + 1) << lsb;
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const u32 exclusion_mask = ~inclusion_mask;
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const IR::U32 operand1 = ir.And(ir.GetRegister(d), ir.Imm32(exclusion_mask));
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const IR::U32 operand2 = ir.And(ir.LogicalShiftLeft(ir.GetRegister(n), ir.Imm8(lsb)), ir.Imm32(inclusion_mask));
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const IR::U32 result = ir.Or(operand1, operand2);
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ir.SetRegister(d, result);
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return true;
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}
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// CLZ<c> <Rd>, <Rm>
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bool ArmTranslatorVisitor::arm_CLZ(Cond cond, Reg d, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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@ -208,6 +208,7 @@ struct ArmTranslatorVisitor final {
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// Miscellaneous instructions
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bool arm_BFC(Cond cond, Imm5 msb, Reg d, Imm5 lsb);
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bool arm_BFI(Cond cond, Imm5 msb, Reg d, Imm5 lsb, Reg n);
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bool arm_CLZ(Cond cond, Reg d, Reg m);
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bool arm_NOP() { return true; }
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bool arm_RBIT(Cond cond, Reg d, Reg m);
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@ -1080,7 +1080,7 @@ TEST_CASE("VFP: VPUSH, VPOP", "[JitX64][.vfp][A32]") {
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}
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TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
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const auto is_bfc_valid = [](u32 instr) {
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const auto is_bfc_bfi_valid = [](u32 instr) {
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if (Bits<12, 15>(instr) == 0b1111) {
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// Destination register may not be the PC.
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return false;
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@ -1095,8 +1095,9 @@ TEST_CASE("Test ARM misc instructions", "[JitX64][A32]") {
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};
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const std::array instructions = {
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InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_valid), // BFC
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InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ
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InstructionGenerator("cccc0111110vvvvvddddvvvvv0011111", is_bfc_bfi_valid), // BFC
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InstructionGenerator("cccc0111110vvvvvddddvvvvv001nnnn", is_bfc_bfi_valid), // BFI
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InstructionGenerator("cccc000101101111dddd11110001mmmm", is_clz_valid), // CLZ
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};
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FuzzJitArm(1, 1, 10000, [&instructions]() -> u32 {
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