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A32: Implement ASIMD VPADDL (integer)

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Lioncash 2020-06-20 15:39:41 -04:00 committed by merry
parent 4bb286ac23
commit 266c6a2000
3 changed files with 23 additions and 1 deletions
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2
src/frontend/A32/decoder/asimd.inc
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@ -81,7 +81,7 @@ INST(asimd_VSLI, "VSLI", "111100111Diiiiiidddd010
// Two registers, miscellaneous
INST(asimd_VREV, "VREV{16,32,64}", "111100111D11zz00dddd000ooQM0mmmm") // ASIMD
//INST(asimd_VPADDL, "VPADDL", "111100111-11--00----0010xx-0----") // ASIMD
INST(asimd_VPADDL, "VPADDL", "111100111D11zz00dddd0010oQM0mmmm") // ASIMD
INST(asimd_VCLS, "VCLS", "111100111D11zz00dddd01000QM0mmmm") // ASIMD
INST(asimd_VCLZ, "VCLZ", "111100111D11zz00dddd01001QM0mmmm") // ASIMD
INST(asimd_VCNT, "VCNT", "111100111D11zz00dddd01010QM0mmmm") // ASIMD

21
src/frontend/A32/translate/impl/asimd_two_regs_misc.cpp
View file

@ -129,6 +129,27 @@ bool ArmTranslatorVisitor::asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, b
return true;
}
bool ArmTranslatorVisitor::asimd_VPADDL(bool D, size_t sz, size_t Vd, bool op, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();
}
if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) {
return UndefinedInstruction();
}
const size_t esize = 8U << sz;
const auto d = ToVector(Q, Vd, D);
const auto m = ToVector(Q, Vm, M);
const auto reg_m = ir.GetVector(m);
const auto result = op ? ir.VectorPairedAddUnsignedWiden(esize, reg_m)
: ir.VectorPairedAddSignedWiden(esize, reg_m);
ir.SetVector(d, result);
return true;
}
bool ArmTranslatorVisitor::asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm) {
if (sz == 0b11) {
return UndefinedInstruction();

1
src/frontend/A32/translate/impl/translate_arm.h
View file

@ -492,6 +492,7 @@ struct ArmTranslatorVisitor final {
// Advanced SIMD two register, miscellaneous
bool asimd_VREV(bool D, size_t sz, size_t Vd, size_t op, bool Q, bool M, size_t Vm);
bool asimd_VPADDL(bool D, size_t sz, size_t Vd, bool op, bool Q, bool M, size_t Vm);
bool asimd_VCLS(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VCLZ(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);
bool asimd_VCNT(bool D, size_t sz, size_t Vd, bool Q, bool M, size_t Vm);